Mini IOM-2 Controller MICO

Overview The Mini IOM-2 Controller MICO (PEF 2015) is an interface controller optimized for small line card applications or Intelligent NTs. It is derived from the EPIC core. The MICO supports up to 16 analog subscribers (up to 8 using the SLICOFI) or up to 8 ISDN-BA subscribers. Features Funct

ICs for Communications

Overview The Mini IOM-2 Controller MICO (PEF 2015) is an interface controller optimized for small line card applications or Intelligent NTs. It is derived from the EPIC core. The MICO supports up to 16 analog subscribers (up to 8 using the SLICOFI) or up to 8 ISDN-BA subscribers. Features Funct

ISDN DC Converter Circuit IDCC

Overview The PEB/F 2023 is a pulse width modulator circuit designed for fixed-frequency switching regulators with very low power consumption. In telephone and ISDN-systems a high conversion yield is crucial to maintain functionality in all supply conditions via S- or U-interfaces. The PEB/F 2023

Multichannel Network Interface Controller for HDLC

Overview The MUNICH32X is an enhanced version of the Multichannel Network Interface Controller for HDLC, MUNICH32 (PEB 20320, refer to the User’s Manual 01.2000). Key enhancements include: • a 33 MHz/32-bit PCI bus Master/Slave interface with integrated DMA controllers for higher performance, l

ICs for Communications

Introduction The MUNICH128X is a 128-channel WAN Protocol Controller which provides four independent 24/32-channel HDLC controllers, each with a dedicated 64-channel DMA Controller and a Serial PCM Interface Controller. The device is offered in a 160- pin MQFP package, making it ideal for high-po

Memory Time Switch CMOS (MTSC)

Features ● Time/space switch for 2048-, 4096- or 8192-kbit/s PCM systems ● Switching of up to 512 incoming PCM channels to up to 256 outgoing PCM channels ● 16-input and 8-output PCM lines ● Different kinds of modes (2048, 4096, 8192 kbit/s or mixed mode) ● Configurable for primary access and

Memory Time Switch CMOS (MTSC)

Features ● Time/space switch for 2048-, 4096- or 8192-kbit/s PCM systems ● Switching of up to 512 incoming PCM channels to up to 256 outgoing PCM channels ● 16-input and 8-output PCM lines ● Different kinds of modes (2048, 4096, 8192 kbit/s or mixed mode) ● Configurable for primary access and

Memory Time Switch CMOS (MTSC)

Features ● Time/space switch for 2048-, 4096- or 8192-kbit/s PCM systems ● Switching of up to 512 incoming PCM channels to up to 256 outgoing PCM channels ● 16-input and 8-output PCM lines ● Different kinds of modes (2048, 4096, 8192 kbit/s or mixed mode) ● Configurable for primary access and

Memory Time Switch Large MTSL

General Device Overview The Siemens Memory Time Switch Large MTSL (PEB 2047) is an expansion of the MTSC (PEB 2045) regarding capacity and/or functionality. It is a monolithic CMOS switching device capable of connecting maximally 1024 PCM-input time-slots to 1024 output time-slots. Features ●

2 Channel Serial Optimized Communication Controller for HDLC/PPP

Introduction The SEROCCO-H is a Serial Communication Controller with two independent serial channels1). The serial channels are derived from updated protocol logic of the ESCC and DSCC4 device family providing a large set of protocol support and variety in serial interface configuration. This all

2 Channel Serial Optimized Communication Controller

Introduction The SEROCCO-M is a Serial Communication Controller with two independent serial channels1). The serial channels are derived from updated protocol logic of the ESCC and DSCC4 device family providing a large set of protocol support and variety in serial interface configuration. This a

DMA Supported Serial Communication Controller with 4 Channels

Overview The DSCC4 is a DMA Supported Serial Communication Controller with four independent serial channels1). The serial channels are derived from updated protocol logic of the ESCC device family providing a large set of protocol support and variety in serial interface configuration. This allows

ICs for Communications

Overview The PEB 2055 (Extended PCM Interface Controller) is a highly integrated controller circuit optimized for analog and ISDN line card and central switches applications. The EPIC-1 provides the circuitry necessary to manage up to 32 digital (ISDN or proprietary) or 64 analog subscribers. Th

2 Channel Serial Optimized Communication Controller with DMA

Introduction The SEROCCO-D is a DMA Integrated Serial Communication Controller with two independent serial channels1). The serial channels are derived from updated protocol logic of the ESCC and DSCC4 device family providing a large set of protocol support and variety in serial interface config

ICs for Communications

Overview The PEB 2055 (Extended PCM Interface Controller) is a highly integrated controller circuit optimized for analog and ISDN line card and central switches applications. The EPIC-1 provides the circuitry necessary to manage up to 32 digital (ISDN or proprietary) or 64 analog subscribers. Th

ICs for Communications

Overview The PEB 20550 (Extended Line Card Controller) is a highly integrated controller circuit optimized for line card and key system applications. It combines all functional blocks necessary to manage up to 32 digital (ISDN or proprietary) or 64 analog subscribers. The switching and layer-1 c

DSP Embedded Line and Port Interface Controller

Addendum to “DELIC Clock System Synchronization” The DELIC Clock System Synchronization is described in the DELIC-LC PEB 20570/DELIC-PB PEB 20571 Data Sheet, independent of the version (2.1 .. 3.1). As an addendum to chapter “DELIC Clock System Synchronization” of the DELICLC/DELIC-PB Data Sheet

DSP Embedded Line and Port Interface Controller

Addendum to “DELIC Clock System Synchronization” The DELIC Clock System Synchronization is described in the DELIC-LC PEB 20570/DELIC-PB PEB 20571 Data Sheet, independent of the version (2.1 .. 3.1). As an addendum to chapter “DELIC Clock System Synchronization” of the DELICLC/DELIC-PB Data Sheet

S/T Bus Interface Circuit (SBC)

The S-Bus Interface Circuit (SBC) PEx 2080 implements the four-wire S/T-interface used to link voice/data terminals to an ISDN. Through selection of operating mode, the device may be employed in all types of applications involving an S interface. Two or more SBC´s can be used to build a point to-p

Smart Integrated Digital Echo Canceller

Introduction The Smart Integrated Digital Echo Canceller (SIDEC) suppresses echoes in telecommunication networks which might disturb any kind of terrestrial or wireless communication. It incorporates leading edge CMOS technology as well as INFINEON’s many years experience in Telecommunication ICs

RF Power Plate Capacitors for Higher Voltages Class 1 Ceramic

• Low losses • High reliability • High voltage ratings

Quad E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

Abstract This document is an Addendumto the PEF 22554 HT/E, QuadFALC®, Version 2.1 Data Sheet DS1, release date 2002-09. It describes data that has to be changed or added.

Quad E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

Abstract This document is an Addendumto the PEF 22554 HT/E, QuadFALC®, Version 2.1 Data Sheet DS1, release date 2002-09. It describes data that has to be changed or added.

Quad E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

Abstract This document is an Addendumto the PEF 22554 HT/E, QuadFALC®, Version 2.1 Data Sheet DS1, release date 2002-09. It describes data that has to be changed or added.

E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications

Introduction The FALC®56 framer and line interface component is designed to fulfill all required interfacing between analog E1/T1/J1 lines and the digital PCM system highway, H.100/H.110 or H-MVIP bus for world market telecommunication systems. Features Line Interface • High-density, generic i

E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications

Introduction The FALC®56 framer and line interface component is designed to fulfill all required interfacing between analog E1/T1/J1 lines and the digital PCM system highway, H.100/H.110 or H-MVIP bus for world market telecommunication systems. Features Line Interface • High-density, generic i

E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications

Introduction The FALC®56 framer and line interface component is designed to fulfill all required interfacing between analog E1/T1/J1 lines and the digital PCM system highway, H.100/H.110 or H-MVIP bus for world market telecommunication systems. Features Line Interface • High-density, generic i

E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications

Introduction The FALC®56 framer and line interface component is designed to fulfill all required interfacing between analog E1/T1/J1 lines and the digital PCM system highway, H.100/H.110 or H-MVIP bus for world market telecommunication systems. Features Line Interface • High-density, generic i

Four Channel Codec Filter with PCM and Microcontroller Interface

General Description The four channel Signal Processing Codec Filter PEB 2466 SICOFI-4-µC is the logical continuation of a well established family of SIEMENS programmable codec-filter-ICs. Its major difference to the PEB 2465 (SICOFI-4) is the PCM and µC interface, which replaces the IOM-2 interf

Quad ISDN Echocancellation Circuit Analog Front End for Splitterless ADSL over ISDN

Overview The IEC-4-AFE-X Version 3.2 is part of Infineon´s chip set for a splitterless, FDD (non-overlapped) ADSL over ISDN linecard based on GEMINAX MAX according to Ref [3.], chapter 4.2.2 of Ref [5.], Annex B of Ref [6.] / Ref [7.], and Ref [8.]. Figure 1 shows the basic architecture of an in

Multichannel Network Interface Controller for HDLC/PPP

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封装/外壳：20-SOIC（0.433"，11.00mm 宽）裸露焊盘 功能：高压电源控制器 包装：托盘 描述：IC TELECOM INTERFACE PDSO-20 集成电路（IC） 电信

IC NETWORK TERMINATOR PDSO-20

Switching IC

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Switching IC

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Switching IC

Switching IC

文件：2.50944 Mbytes Page：129 Pages

Switching IC

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2通道串行优化的通信控制器的HDLC / PPP [2 Channel Serial Optimized Communication Controller for HDLC/PPP]

Plate Capacitors with Moisture Protection Plate Capacitors for Higher Voltages

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RF Power Plate Capacitors for Higher Voltages Class 1 Ceramic

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RF Power Plate Capacitors for Higher Voltages Class 1 Ceramic

文件：104.35 Kbytes Page：7 Pages

RF Power Plate Capacitors for Higher Voltages Class 1 Ceramic

文件：104.35 Kbytes Page：7 Pages

RF Power Plate Capacitors for Higher Voltages Class 1 Ceramic

文件：104.35 Kbytes Page：7 Pages

RF Power Plate Capacitors for Higher Voltages Class 1 Ceramic

文件：104.35 Kbytes Page：7 Pages

RF Power Plate Capacitors for Higher Voltages Class 1 Ceramic

文件：104.35 Kbytes Page：7 Pages

RF Power Plate Capacitors for Higher Voltages Class 1 Ceramic

文件：104.35 Kbytes Page：7 Pages

RF Power Plate Capacitors for Higher Voltages Class 1 Ceramic

文件：104.35 Kbytes Page：7 Pages

RF Power Plate Capacitors for Higher Voltages Class 1 Ceramic

文件：104.35 Kbytes Page：7 Pages

RF Power Plate Capacitors for Higher Voltages Class 1 Ceramic

文件：104.35 Kbytes Page：7 Pages

RF Power Plate Capacitors for Higher Voltages Class 1 Ceramic

文件：104.35 Kbytes Page：7 Pages

RF Power Plate Capacitors for Higher Voltages Class 1 Ceramic

文件：104.35 Kbytes Page：7 Pages

RF Power Plate Capacitors for Higher Voltages Class 1 Ceramic

文件：104.35 Kbytes Page：7 Pages

RF Power Plate Capacitors for Higher Voltages Class 1 Ceramic

文件：104.35 Kbytes Page：7 Pages

RF Power Plate Capacitors for Higher Voltages Class 1 Ceramic

文件：104.35 Kbytes Page：7 Pages

RF Power Plate Capacitors for Higher Voltages Class 1 Ceramic

文件：104.35 Kbytes Page：7 Pages

RF Power Plate Capacitors for Higher Voltages Class 1 Ceramic

文件：104.35 Kbytes Page：7 Pages

RF Power Plate Capacitors for Higher Voltages Class 1 Ceramic

文件：104.35 Kbytes Page：7 Pages

RF Power Plate Capacitors for Higher Voltages Class 1 Ceramic

文件：104.35 Kbytes Page：7 Pages

RF Power Plate Capacitors for Higher Voltages Class 1 Ceramic

文件：104.35 Kbytes Page：7 Pages