丝印代码：011101；50 V, 500 mA NPN resistor-equipped transistors

General description NPN Resistor-Equipped Transistor (RET) family in a leadless ultra small DFN1010D-3 (SOT1215) Surface-Mounted Device (SMD) plastic package with visible and solderable side pads. Features and benefits ■ 500 mA output current capability ■ Reduced pick and place costs ■ Built

丝印代码：011101；50 V, 500 mA NPN resistor-equipped transistors

Features and benefits  500 mA output current capability  Built-in bias resistors   10 resistor ratio tolerance  Simplifies circuit design  Reduces component count  Reduced pick and place costs  Low package height of 0.37 mm  Suitable for Automatic Optical Inspection (AOI) of sold

50 V, 500 mA PNP resistor-equipped transistors

Features and benefits  500 mA output current capability  Built-in bias resistors   10 resistor ratio tolerance  Simplifies circuit design  Reduces component count  Reduced pick and place costs  Low package height of 0.37 mm  Suitable for Automatic Optical Inspection (AOI) of sold

50 V, 500 mA NPN resistor-equipped transistors

NPN Resistor-Equipped Transistor (RET) family in a leadless ultra small DFN1010D-3 (SOT1215) Surface-Mounted Device (SMD) plastic package with visible and solderable side pads.\nTable 1. Product overview Type mumber\n R1\n R2\n Package Nexperia\n PNP complement\n PDTD113EQA\n 1 • 500 mA output current capability\n• Built-in bias resistors\n• ±10 % resistor ratio tolerance\n• Simplifies circuit design\n• Reduces component count\n• Reduced pick and place costs\n• Low package height of 0.37 mm\n• Suitable for Automatic Optical Inspection (AOI) of solder joint\n• AEC-Q101 ;

封装/外壳：3-XDFN 裸露焊盘 包装：卷带（TR） 描述：TRANS PREBIAS NPN 3DFN 分立半导体产品 晶体管 - 双极（BJT）- 单，预偏置

PNP SILICON BIAS RESISTOR TRANSISTOR

This new series of digital transistors is designed to replace a single device and its external resistor bias network. The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. The

Bias Resistor Transistor PNP Silicon Surface Mount Transistor with Monolithic Bias Resistor Network

The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. These digital transistors are designed to replace a single device and its xternal resistor bias network. The BRT eliminate

CASE 463-01, STYLE 1 SOT-416/SC-90

The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. These digital transistors are designed to replace a single device and its external resistor bias network. The BRT eliminat

CASE 463-01, STYLE 1 SOT-416/SC-90

Bias Resistor Transistor NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. These digital trans

0.25關m Sea of Gates and Customer Structured Arrays

DESCRIPTION Oki’s 0.25µm Application-Specific Integrated Circuit (ASIC) products are available in both Sea Of Gates (SOG) and Customer Structured Array (CSA) architectures. Both the SOG-based MG115P series and the CSA-based MG75P series use a five-layer metal process on 0.25µm drawn (0.18µm L-eff