NPN resistor-equipped transistor; R1 = 10 k廓, R2 = 10 k廓

丝印代码：01001010；NPN resistor-equipped transistor; R1 = 10 kΩ, R2 = 10 kΩ

Features and benefits  100 mA output current capability  Reduces component count  Built-in bias resistors  Reduces pick and place costs  Simplifies circuit design  AEC-Q101 qualified  Leadless ultra small SMD plastic package  Low package height of 0.37 mm

NPN resistor-equipped transistor; R1 = 10 kΩ, R2 = 10 kΩ

NPN resistor-equipped transistor; R1 = 10 kΩ, R2 = 10 kΩ

封装/外壳：3-XFDFN 包装：卷带（TR） 描述：TRANS PREBIAS NPN 50V DFN1006B-3 分立半导体产品 晶体管 - 双极（BJT）- 单，预偏置

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Bias Resistor Transistor PNP Silicon Surface Mount Transistor with Monolithic Bias Resistor Network

The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. These digital transistors are designed to replace a single device and its xternal resistor bias network. The BRT eliminate

CASE 463-01, STYLE 1 SOT-416/SC-90

The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. These digital transistors are designed to replace a single device and its external resistor bias network. The BRT eliminat

CASE 463-01, STYLE 1 SOT-416/SC-90

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0.25關m Sea of Gates and Customer Structured Arrays

DESCRIPTION Oki’s 0.25µm Application-Specific Integrated Circuit (ASIC) products are available in both Sea Of Gates (SOG) and Customer Structured Array (CSA) architectures. Both the SOG-based MG115P series and the CSA-based MG75P series use a five-layer metal process on 0.25µm drawn (0.18µm L-eff