丝印代码：110111；50 V, 100 mA PNP resistor-equipped transistors

General description 100 mA PNP Resistor-Equipped Transistor (RET) family in a leadless ultra small DFN1010D-3 (SOT1215) Surface-Mounted Device (SMD) plastic package with visible and solderable side pads. Features and benefits ■ 100 mA output current capability ■ reduced pick and place costs

50 V, 100 mA NPN resistor-equipped transistors

Features and benefits  100 mA output current capability  Built-in bias resistors  Simplifies circuit design  Reduces component count  Reduced pick and place costs  Low package height of 0.37 mm  AEC-Q101 qualified  Suitable for Automatic Optical Inspection (AOI) of solder joint

丝印代码：110111；50 V, 100 mA PNP resistor-equipped transistors

Features and benefits  100 mA output current capability  built-in bias resistors  simplifies circuit design  reduces component count  reduced pick and place costs  low package height of 0.37 mm  AEC-Q101 qualified  suitable for Automatic Optical Inspection (AOI) of solder joint

丝印代码：110111；50 V, 100 mA PNP resistor-equipped transistors

1.1 General description 100 mA PNP Resistor-Equipped Transistor (RET) family in a leadless ultra small DFN1010D-3 (SOT1215) Surface-Mounted Device (SMD) plastic package with visible and solderable side pads. 1.2 Features and benefits 1.3 Applications Table 1. Product overview Type number R1

50 V, 100 mA PNP resistor-equipped transistors

100 mA PNP Resistor-Equipped Transistor (RET) family in a leadless ultra small DFN1010D-3 (SOT1215) Surface-Mounted Device (SMD) plastic package with visible and solderable side pads. • 100 mA output current capability\n• Built-in bias resistors\n• Simplifies circuit design\n• Reduces component count\n• Reduced pick and place costs\n• Low package height of 0.37 mm\n• AEC-Q101 qualified\n• Suitable for Automatic Optical Inspection (AOI) of solder joint;

封装/外壳：3-XDFN 裸露焊盘 包装：卷带（TR） 描述：TRANS PREBIAS PNP 3DFN 分立半导体产品 晶体管 - 双极（BJT）- 单，预偏置

PNP SILICON BIAS RESISTOR TRANSISTOR

This new series of digital transistors is designed to replace a single device and its external resistor bias network. The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. The

Bias Resistor Transistor PNP Silicon Surface Mount Transistor with Monolithic Bias Resistor Network

The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. These digital transistors are designed to replace a single device and its xternal resistor bias network. The BRT eliminate

CASE 463-01, STYLE 1 SOT-416/SC-90

The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. These digital transistors are designed to replace a single device and its external resistor bias network. The BRT eliminat

CASE 463-01, STYLE 1 SOT-416/SC-90

Bias Resistor Transistor NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. These digital trans

0.25關m Sea of Gates and Customer Structured Arrays

DESCRIPTION Oki’s 0.25µm Application-Specific Integrated Circuit (ASIC) products are available in both Sea Of Gates (SOG) and Customer Structured Array (CSA) architectures. Both the SOG-based MG115P series and the CSA-based MG75P series use a five-layer metal process on 0.25µm drawn (0.18µm L-eff