丝印代码：E5；PNP resistor-equipped transistors; R1 = 10 k廓, R2 = 10 k廓

丝印代码：E5；50 V, 100 mA PNP resistor-equipped transistor; R1 = 10 kΩ, R2 = 10 kΩ

1. General description PNP Resistor-Equipped Transistor (RET) in a leadless ultra small SOT883 (SC-101) Surface- Mounted Device (SMD) plastic package. NPN complement: PDTC114EM 2. Features and benefits . 100 mA output current capability . Built-in bias resistors . Simplifies circuit desig

NPN resistor-equipped transistors; R1 = 10 k, R2 = 10 k

Features and benefits  100 mA output current capability  Built-in bias resistors  Simplifies circuit design  Reduces component count  Reduces pick and place costs  AEC-Q101 qualified

PNP resistor-equipped transistors; R1 = 10 kΩ; R2 = 10 kΩ

PNP Resistor-Equipped Transistor (RET) family in small Surface-Mounted Device (SMD) plastic packages. • 100 mA output current capability\n• Built-in bias resistors\n• Simplifies circuit design\n• Reduces component count\n• Reduces pick and place costs\n• AEC-Q101 qualified;

PNP resistor-equipped transistor; R1 = 10 kΩ, R2 = 10 kΩ

PNP Resistor-Equipped Transistor (RET) in a leadless ultra small DFN1006B-3 (SOT883B) Surface-Mounted Device (SMD) plastic package. NPN complement: PDTC114EMB • 100 mA output current capability\n• Reduces component count\n• Built-in bias transistors\n• Reduces pick and place costs\n• Simplifies circuit design\n• AEC-Q101 qualified\n• Leadless ultra small SMD plastic package\n• Low package height of 0.37 mm;

丝印代码：00011001；PNP resistor-equipped transistor; R1 = 10 k廓, R2 = 10 k廓

General description PNP Resistor-Equipped Transistor (RET) in a leadless ultra small DFN1006B-3 (SOT883B) Surface-Mounted Device (SMD) plastic package. NPN complement: PDTC114EMB Features and benefits ■ 100 mA output current capability ■ Reduces component count ■ Built-in bias transistors ■

封装/外壳：SC-101，SOT-883 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：TRANS PREBIAS PNP 250MW SOT883 分立半导体产品 晶体管 - 双极（BJT）- 单，预偏置

封装/外壳：3-XFDFN 包装：卷带（TR） 描述：TRANS PREBIAS PNP 50V DFN1006B-3 分立半导体产品 晶体管 - 双极（BJT）- 单，预偏置

PNP SILICON BIAS RESISTOR TRANSISTOR

This new series of digital transistors is designed to replace a single device and its external resistor bias network. The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. The

Bias Resistor Transistor PNP Silicon Surface Mount Transistor with Monolithic Bias Resistor Network

The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. These digital transistors are designed to replace a single device and its xternal resistor bias network. The BRT eliminate

CASE 463-01, STYLE 1 SOT-416/SC-90

The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. These digital transistors are designed to replace a single device and its external resistor bias network. The BRT eliminat

CASE 463-01, STYLE 1 SOT-416/SC-90

Bias Resistor Transistor NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. These digital trans

0.25關m Sea of Gates and Customer Structured Arrays

DESCRIPTION Oki’s 0.25µm Application-Specific Integrated Circuit (ASIC) products are available in both Sea Of Gates (SOG) and Customer Structured Array (CSA) architectures. Both the SOG-based MG115P series and the CSA-based MG75P series use a five-layer metal process on 0.25µm drawn (0.18µm L-eff