位置：首页 > IC中文资料第6337页 > PDSP16112A
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
PDSP16112A | 16 X 12 BIT COMPLEX MULTIPLIER The PDSP16112/PDSP16112A will multply a complex (16+16) bit word by a complex (12+12) bit coefficient word and produce a complex (17+17) bit rounded product. FEATURES ■ 20MHz Complex Number (16+16) x (12+12) Multplication ■ Pipeline Architecture ■ Power Dissipation only 500mW ■ TTL Compatible | ZARLINK Zarlink Semiconductor Inc |   | |
PDSP16112A | 16 by 16 Bit Complex Multiplier The PDSP16116A will multiply two complex (16 + 16) bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional twos complement. FEATURES ■ Complex Number (16 + 16) X (16 + 16) Multiplication ■ Full 32 bit Re | ZARLINK Zarlink Semiconductor Inc | | |
16 X 12 BIT COMPLEX MULTIPLIER The PDSP16112/PDSP16112A will multply a complex (16+16) bit word by a complex (12+12) bit coefficient word and produce a complex (17+17) bit rounded product. FEATURES ■ 20MHz Complex Number (16+16) x (12+12) Multplication ■ Pipeline Architecture ■ Power Dissipation only 500mW ■ TTL Compatible | ZARLINK Zarlink Semiconductor Inc | | ||
16 X 12 BIT COMPLEX MULTIPLIER The PDSP16112/PDSP16112A will multply a complex (16+16) bit word by a complex (12+12) bit coefficient word and produce a complex (17+17) bit rounded product. FEATURES ■ 20MHz Complex Number (16+16) x (12+12) Multplication ■ Pipeline Architecture ■ Power Dissipation only 500mW ■ TTL Compatible | ZARLINK Zarlink Semiconductor Inc | | ||
16 X 12 BIT COMPLEX MULTIPLIER The PDSP16112/PDSP16112A will multply a complex (16+16) bit word by a complex (12+12) bit coefficient word and produce a complex (17+17) bit rounded product. FEATURES ■ 20MHz Complex Number (16+16) x (12+12) Multplication ■ Pipeline Architecture ■ Power Dissipation only 500mW ■ TTL Compatible | ZARLINK Zarlink Semiconductor Inc | | ||
16 X 12 BIT COMPLEX MULTIPLIER The PDSP16112/PDSP16112A will multply a complex (16+16) bit word by a complex (12+12) bit coefficient word and produce a complex (17+17) bit rounded product. FEATURES ■ 20MHz Complex Number (16+16) x (12+12) Multplication ■ Pipeline Architecture ■ Power Dissipation only 500mW ■ TTL Compatible | ZARLINK Zarlink Semiconductor Inc | | ||
16 X 12 BIT COMPLEX MULTIPLIER The PDSP16112/PDSP16112A will multply a complex (16+16) bit word by a complex (12+12) bit coefficient word and produce a complex (17+17) bit rounded product. FEATURES ■ 20MHz Complex Number (16+16) x (12+12) Multplication ■ Pipeline Architecture ■ Power Dissipation only 500mW ■ TTL Compatible | ZARLINK Zarlink Semiconductor Inc | | ||
16 X 12 BIT COMPLEX MULTIPLIER The PDSP16112/PDSP16112A will multply a complex (16+16) bit word by a complex (12+12) bit coefficient word and produce a complex (17+17) bit rounded product. FEATURES ■ 20MHz Complex Number (16+16) x (12+12) Multplication ■ Pipeline Architecture ■ Power Dissipation only 500mW ■ TTL Compatible | ZARLINK Zarlink Semiconductor Inc | | ||
16 X 12 BIT COMPLEX MULTIPLIER The PDSP16112/PDSP16112A will multply a complex (16+16) bit word by a complex (12+12) bit coefficient word and produce a complex (17+17) bit rounded product. FEATURES ■ 20MHz Complex Number (16+16) x (12+12) Multplication ■ Pipeline Architecture ■ Power Dissipation only 500mW ■ TTL Compatible | ZARLINK Zarlink Semiconductor Inc | | ||
16 X 12 BIT COMPLEX MULTIPLIER The PDSP16112/PDSP16112A will multply a complex (16+16) bit word by a complex (12+12) bit coefficient word and produce a complex (17+17) bit rounded product. FEATURES ■ 20MHz Complex Number (16+16) x (12+12) Multplication ■ Pipeline Architecture ■ Power Dissipation only 500mW ■ TTL Compatible | ZARLINK Zarlink Semiconductor Inc | | ||
16 by 16 Bit Complex Multiplier The PDSP16116A will multiply two complex (16 + 16) bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional twos complement. FEATURES ■ Complex Number (16 + 16) X (16 + 16) Multiplication ■ Full 32 bit Re | ZARLINK Zarlink Semiconductor Inc | | ||
Complex Accumulator The PDSP16318 contains two independent 20-bit Adder/Subtractors combined with accumulator registers and shift structures. The four port architecture permits full 10MHz throughout in FFT and filter applications. Two PDSP16318s combined with a single PDSP16112A Complex Multiplier provide a complete | ZARLINK Zarlink Semiconductor Inc | | ||
16 X 12 BIT COMPLEX MULTIPLIER The PDSP16112/PDSP16112A will multply a complex (16+16) bit word by a complex (12+12) bit coefficient word and produce a complex (17+17) bit rounded product. FEATURES ■ 20MHz Complex Number (16+16) x (12+12) Multplication ■ Pipeline Architecture ■ Power Dissipation only 500mW ■ TTL Compatible | ZARLINK Zarlink Semiconductor Inc | | ||
9600/14400 bps FAX MODEM 文件：513.58 Kbytes Page：69 Pages | SAMSUNG 三星 | |
PDSP16112A产品属性
- 类型
描述
- 型号
PDSP16112A
- 功能描述
Logic IC
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
ZARLINK |
QQ咨询 |
PGA |
824 |
全新原装 研究所指定供货商 |
|||
ZARLINK |
24+ |
56 |
宇航级进口原装正品现货质量保证! |
||||
ZARLINK |
10+ |
原厂封装 |
56 |
宇航IC只做原装假一罚十 |
|||
24+ |
QFP |
3000 |
公司存货 |
||||
GPS |
24+ |
PGA |
80000 |
只做自己库存 全新原装进口正品假一赔百 可开13%增 |
|||
GPS |
24+ |
PGA |
200 |
进口原装正品优势供应 |
|||
GPS |
2318+ |
PGA |
4862 |
只做进口原装!假一赔百!自己库存价优! |
|||
- |
23+ |
NA |
98000 |
原厂授权一级代理,专业海外优势订货,价格优势、品种 |
|||
ZARLINK |
18+ |
原厂原装假一赔十 |
20 |
原厂很远现货很近,找现货选星佑电子,原厂原装假一赔 |
|||
25+ |
长期备有现货 |
500000 |
行业低价,代理渠道 |
PDSP16112A芯片相关品牌
PDSP16112A规格书下载地址
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DdatasheetPDF页码索引
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