The PDSP16112/PDSP16112A will multply a complex (16+16) bit word by a complex (12+12) bit coefficient word and produce a complex (17+17) bit rounded product.

FEATURES

■ 20MHz Complex Number (16+16) x (12+12) Multplication

■ Pipeline Architecture

■ Power Dissipation only 500mW

■ TTL Compatible Inputs

■ 120 Pin PGA or QFP packages

APPLICATIONS

■ Digital Filtering

■ Fast Fourier Transforms

■ Radar and Sonar Processing

■ Instrumentation

■ Automation

■ Image Processing