66-150MHz Phase Locked Loop Differential 1:10 SDRAM Clock Driver

DESCRIPTION Zero delay buffer to distribute an SSTL differential clock input pair to 10 SSTL_2 differential output pairs. Outputs are slope controlled. External feedback pin for synchronization of the outputs to the input. A CMOS style Enable/Disable pin is provided for low power disable. FEAT

封装/外壳：48-TFSOP（0.240"，6.10mm 宽） 包装：托盘 描述：IC CLK BUF DDR 167MHZ 1CIRC 集成电路（IC） 应用特定时钟/定时

封装/外壳：48-TFSOP（0.240"，6.10mm 宽） 包装：托盘 描述：IC CLK BUF DDR 167MHZ 1CIRC 集成电路（IC） 应用特定时钟/定时

857 Series High Temp Card Edge Connector | Black | 0.156 (3.96mm) Pitch | 0.200 (5.08mm) Row Spacing | Low Profile Insulator

Features 0.156 (3.96mm) Contact Spacing by 0.200 (5.08mm) Row Spacing Accepts .062 (1.57mm) Nominal Thickness P.C. Board Low Profile Insulator Body, 0.473 (12.01mm) Contact Termination Options include P.C. Tail, Wire Hole, Wire Wrap, 90 and Extender Board Bends Single or Dual Row Configuratio

General Purpose Transistor

Features - Low current (max. 100mA). - Low voltage. - AEC-Q101 Qualified.

General Purpose Transistor

Features - For AF input stages and driver applications. - High current gain. - Low collector-emitter saturation voltage. - Low noise between 30Hz and 15kHz. - AEC-Q101 Qualified.

General Purpose Transistor

Features - Low current (max. 100mA). - Low voltage. - AEC-Q101 Qualified.

boxes and ancillary products

文件：3.51246 Mbytes Page：5 Pages