Hot swappable I2C-bus and SMBus bus buffer

General description The PCA9511A is a hot swappable I2C-bus and SMBus buffer that allows I/O card insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the b

Hot swappable I2C-bus and SMBus bus buffer

Hot Swappable I2C-Bus and SMBus Bus Buffer

Hot Swappable I2C-Bus and SMBus Bus Buffer The PCA9511A is a hot swappable I2C−bus and SMBus buffer that allows I/O card insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from being connected to the card until a stop command or b

Hot swappable I2C-bus and SMBus bus buffer Rev. 04 ??19 August 2009

Smart, simple solutions for the 12 most common design concerns

PCA9511A: Hot Swappable I2C-Bus and SMBus Bus Buffer

Hot swappable I2C-bus and SMBus bus buffer

Hot swappable I2C-bus and SMBus bus buffer

General description The PCA9511A is a hot swappable I2C-bus and SMBus buffer that allows I/O card insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the b

Hot Swappable I2C-Bus and SMBus Bus Buffer

Hot Swappable I2C-Bus and SMBus Bus Buffer The PCA9511A is a hot swappable I2C−bus and SMBus buffer that allows I/O card insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from being connected to the card until a stop command or b

Hot swappable I2C-bus and SMBus bus buffer

Hot swappable I2C-bus and SMBus bus buffer

General description The PCA9511A is a hot swappable I2C-bus and SMBus buffer that allows I/O card insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the b

Hot Swappable I2C-Bus and SMBus Bus Buffer

Hot Swappable I2C-Bus and SMBus Bus Buffer The PCA9511A is a hot swappable I2C−bus and SMBus buffer that allows I/O card insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from being connected to the card until a stop command or b

Hot swappable I2C-bus and SMBus bus buffer

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC BUFFER I2C/SMBUS HOTSWAP 8SO 集成电路（IC） 信号缓冲器、中继器、分离器

Hot swappable I2C-bus and SMBus bus buffer Rev. 04 ??19 August 2009

Hot swappable I2C-bus and SMBus bus buffer

封装/外壳：8-TSSOP，8-MSOP（0.118"，3.00mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC ACCELERATR I2C HOTSWAP 8TSSOP 集成电路（IC） 信号缓冲器、中继器、分离器

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs

GENERAL DESCRIPTION The AD9511 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs

GENERAL DESCRIPTION The AD9511 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs

GENERAL DESCRIPTION The AD9511 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs

GENERAL DESCRIPTION The AD9511 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

MACHINE SCREW PAN PHILLIPS 10-32

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