位置：首页 > IC中文资料第637页 > PA7572J-20L
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
PA7572J-20L | Programmable Electrically Erasable Logic Array General Description The PA7572 is a member of the Programmable Electrically Erasable Logic (PEEL™) Array family based on Anachip’s CMOS EEPROM technology. PEEL™ Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today’s prog | ANACHIP 易亨电子 |   | |
Programmable Electrically Erasable Logic Array General Description The PA7572 is a member of the Programmable Electrically Erasable Logic (PEEL™) Array family based on Anachip’s CMOS EEPROM technology. PEEL™ Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today’s prog | ANACHIP 易亨电子 | |
PA7572J-20L产品属性
- 类型
描述
- 型号
PA7572J-20L
- 功能描述
CPLD - 复杂可编程逻辑器件 14 Input 24 I/O 20ns
- RoHS
否
- 制造商
Lattice
- 存储类型
EEPROM
- 大电池数量
128
- 最大工作频率
333 MHz
- 延迟时间
2.7 ns
- 可编程输入/输出端数量
64
- 工作电源电压
3.3 V
- 最大工作温度
+ 90 C
- 最小工作温度
0 C
- 封装/箱体
TQFP-100
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
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2026+ |
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68500 |
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25+ |
DIP40 |
3629 |
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PA7572J-20L规格书下载地址
PA7572J-20L参数引脚图相关
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DdatasheetPDF页码索引
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