MC74HC595ADTR2G现货供应商，禾融盛电子 13713803681黄先生
MC74HC595ADTR2G功能：
MC74HC595ADTR2G参数：
MC74HC595ADTR2G性能：
? Output Drive Capability: 15 LSTTL Loads
? Outputs Directly Interface to CMOS， NMOS， and_TTL
? Operating Voltage Range: 2.0 to 6.0 V
? Low Input Current: 1.0 ?A
? High Noise Immunity Characteristic of CMOS Devices
? In Compliance with the Requirements Defined by JEDEC
Standard No. 7 A
? Chip Complexity: 328 FETs or 82 Equivalent Gates
? Improvements over HC595
? Improved Propagation Delays
? 50%_Lower Quiescent Power
? Improved Input Noise and_Latchup Immunity
? These Devices are Pb?Free， Halogen Free and_are RoHS Compliant
? NLV Prefix for Automotive and_Other Applications Requiring
Unique Site and_Control Change Requirements;_AEC?Q100
PIN DESCRIPTIONS
INPUTS
A (Pin 14)
Serial Data Input. The data on this pin is shifted into the
8?bit serial shift register.
CONTROL INPUTS
Shift Clock (Pin 11)
Shift Register Clock Input. A low? to?high transition on
this input causes the data at the Serial Input pin to be shifted
into the 8?bit shift register.
Reset (Pin 10)
Active?low， Asynchronous， Shift Register Reset Input. A
low on this pin resets the shift register portion of this device
only. The 8?bit latch is not affected.
Latch Clock (Pin 12)
Storage Latch Clock Input. A low?to?high transition on
this input latches the shift register data.
Output Enable (Pin 13)
Active?low Output Enable. A low on this input allows the
data from the latches to be presented at the outputs. A high
on this input forces the outputs (Q A ?Q H ) into the
high?impedance state. The serial output is not affected by
this control unit.
OUTPUTS
Q A ? Q H (Pins 15， 1， 2， 3， 4， 5， 6， 7)
Noninverted， 3?state， latch outputs.
SQ H (Pin 9)
Noninverted， Serial Data Output. This is the output of the
eighth stage of the 8?bit shift register.
