XC7K160T-2FF676I

时间:2020-6-4 10:52:00

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XC7K160T-2FF676I

制造商编号:

XC7K160T-2FF676I

制造商:Xilinx

说明:

FPGA - 现场可编程门阵列 XC7K160T-2FF676I

寿命周期: 新产品: 此制造商的新产品。

数据表:

XC7K160T-2FF676I 数据表

ECAD模型:XC7K160T-2FF676I ECAD模型下载免费库加载程序,将此文件转换,以供您的ECAD工具使用。了解详情。

更多信息:了解Xilinx XC7K160T-2FF676I详情

规格

产品属性属性值搜索类似

制造商:Xilinx

产品种类:FPGA - 现场可编程门阵列

产品:Kintex-7

逻辑元件数量:162240

输入/输出端数量:400 I/O

工作电源电压:1.2 V to 3.3 V

较小工作温度:- 40 C

较大工作温度:+ 100 C

安装风格:SMD/SMT

封装 / 箱体:FCBGA-676

数据速率:6.6 Gb/s

系列:XC7K160T

商标:Xilinx

分布式RAM:2188 kbit

内嵌式块RAM - EBR:11700 kbit

较大工作频率:640 MHz

湿度敏感性:Yes

收发器数量:8 Transceiver

产品类型:FPGA - Field Programmable Gate Array

工厂包装数量:1

子类别:Programmable Logic ICs

商标名:Kintex

Kintex?-7 FPGA

Xilinx Kintex?-7 FPGA为快速增长应用和无线通信提供较优性价比和低功耗。Kintex-7 FPGA具有卓越的性能和连接性,售价为之前仅限于较高容量应用的价格。

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Mixed-Mode Clock Manager and_Phase-Locked Loop

The MMCM and_PLL share many characteristics. Both can serve as a frequency synthesizer for a wide range of frequencies

and_as a jitter filter for incoming clocks. At the center of both components is a voltage-controlled oscillator (VCO), which

speeds up and_slows down depending on the input voltage it receives from the phase frequency detector (PFD).

There are three sets of programmable frequency dividers: D, M, and_O. The pre-divider D (programmable by configuration

and_afterwards via DRP) reduces the input frequency and_feeds one input of the traditional PLL phase/frequency

comparator. The feedback divider M (programmable by configuration and_afterwards via DRP) acts as a multiplier because

it divides the VCO output frequency before feeding the other input of the phase comparator. D and_M must be chosen

appropriately to keep the VCO within its specified frequency range. The VCO has eight equally-spaced output phases

(0°, 45°, 90°, 135°, 180°, 225°, 270°, and_315°). Each can be selected to drive one of the output dividers (six for the PLL,

O0 to O5, and_seven for the MMCM, O0 to O6), each programmable by configuration to divide by any integer from 1 to 128.

The MMCM and_PLL have three input-jitter filter options: low bandwidth, high bandwidth, or optimized mode. Low-bandwidth

mode has the best jitter attenuation but not the smallest phase offset. High-bandwidth mode has the best phase offset, but

not the best jitter attenuation. Optimized mode allows the tools to find the best setting.

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2024-5-16 15:28:00
供应商 型号 品牌 批号 封装 库存 备注 价格
XILINX
21+
QFP
1280
只做原装,质量保证
XILINX
2016+
BGA
6528
只做进口原装现货!或者订货,假一赔十!
XILINX/赛灵思
2020+
BGA
650
原装现货,优势渠道订货假一赔十
专订XILINX
BGA
2350
一级代理 原装正品假一罚十价格优势长期供货
XILINX
15+
BGA
71
一级代理,专注军工、汽车、医疗、工业、新能源、电力
XILINX
BGA676
58209
16余年资质 绝对原盒原盘 更多数量
XILINX
2020+
FCBGA67
600
只做自己库存,全新原装进口正品假一赔百,可开13%增
XILINX/赛灵思
2324+
BGA
78920
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XILINX
23+
原厂原封
5000
全新原装现货
XILINX
23+
BGA676
8560
受权代理!全新原装现货特价热卖!