2K-Bit Standard 2-Wire Bus Interface

General Description The NM34C02 is 2048 bits of CMOS non-volatile electrically erasable memory. It is designed to support Serial Presence Detect circuitry in memory modules. This communications protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for

2K-Bit Standard 2-Wire Bus Interface

2K-Bit Standard 2-Wire Bus Interface

General Description The NM34C02 is 2048 bits of CMOS non-volatile electrically erasable memory. It is designed to support Serial Presence Detect circuitry in memory modules. This communications protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for

2K-Bit Standard 2-Wire Bus Interface

General Description The NM34C02 is 2048 bits of CMOS non-volatile electrically erasable memory. It is designed to support Serial Presence Detect circuitry in memory modules. This communications protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for

2K-Bit Standard 2-Wire Bus Interface

General Description The NM34C02 is 2048 bits of CMOS non-volatile electrically erasable memory. It is designed to support Serial Presence Detect circuitry in memory modules. This communications protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for

2K-Bit Standard 2-Wire Bus Interface

General Description The NM34C02 is 2048 bits of CMOS non-volatile electrically erasable memory. It is designed to support Serial Presence Detect circuitry in memory modules. This communications protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for

2K-Bit Standard 2-Wire Bus Interface

General Description The NM34C02 is 2048 bits of CMOS non-volatile electrically erasable memory. It is designed to support Serial Presence Detect circuitry in memory modules. This communications protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for

2K-Bit Standard 2-Wire Bus Interface

General Description The NM34C02 is 2048 bits of CMOS non-volatile electrically erasable memory. It is designed to support Serial Presence Detect circuitry in memory modules. This communications protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for

2K-Bit Standard 2-Wire Bus Interface

General Description The NM34C02 is 2048 bits of CMOS non-volatile electrically erasable memory. It is designed to support Serial Presence Detect circuitry in memory modules. This communications protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for

2K-Bit Standard 2-Wire Bus Interface

General Description The NM34C02 is 2048 bits of CMOS non-volatile electrically erasable memory. It is designed to support Serial Presence Detect circuitry in memory modules. This communications protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for

2K-Bit Standard 2-Wire Bus Interface

General Description The NM34C02 is 2048 bits of CMOS non-volatile electrically erasable memory. It is designed to support Serial Presence Detect circuitry in memory modules. This communications protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for

2K-Bit Standard 2-Wire Bus Interface

General Description The NM34C02 is 2048 bits of CMOS non-volatile electrically erasable memory. It is designed to support Serial Presence Detect circuitry in memory modules. This communications protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for

2K-Bit Standard 2-Wire Bus Interface

General Description The NM34C02 is 2048 bits of CMOS non-volatile electrically erasable memory. It is designed to support Serial Presence Detect circuitry in memory modules. This communications protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for

2K-Bit Standard 2-Wire Bus Interface

General Description The NM34C02 is 2048 bits of CMOS non-volatile electrically erasable memory. It is designed to support Serial Presence Detect circuitry in memory modules. This communications protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for

2-Wire Serial EEPROM with Permanent Software Write Protect

Description The AT34C02 provides 2048 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 256 words of 8 bits each. The first-half of the device incorporates a software write protection feature while hardware write protection for the entire array is availa

Two-wire Serial EEPROM with Permanent Software Write Protect

Description The AT34C02 provides 2048 bits of serial electrically-erasable and programmable read only memory (EEPROM) organized as 256 words of 8 bits each. The first-half of the device incorporates a software write protection feature while hardware write protection for the entire array is availa

Two-wire Serial EEPROM with Permanent and Reversible Software Write Protect

Description The AT34C02B provides 2048 bits of serial electrically-erasable and programmable read only memory (EEPROM) organized as 256 words of 8 bits each. The first-half of the device incorporates a permanent and a reversible software write protection feature while hardware write protection fo

Two-wire Serial EEPROM with Permanent and Reversible Software Write Protect

Description The AT34C02C provides 2048 bits of serial electrically-erasable and programmable read only memory (EEPROM) organized as 256 words of 8 bits each. The first-half of the device incorporates a permanent and a reversible software write protection feature while hardware write protection fo

Two-wire Serial EEPROM with Permanent and Reversible Software Write Protect 2K (256 x 8)

Description The AT34C02C provides 2048 bits of serial electrically-erasable and programmable read only memory (EEPROM) organized as 256 words of 8 bits each. The first-half of the device incorporates a permanent and a reversible software write protection feature while hardware write protection fo