N-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description These logic level N-Channel enhancement mode power field effect transistors are produced using Fairchilds proprietary, high cell density, DMOS technology. This very high density process has been especially tailored to minimize on-state resistance, provide superior switching pe

isc N-Channel MOSFET Transistor

FEATURES ·Drain Current -ID= 15A@ TC=25℃ ·Drain Source Voltage -VDSS= 50V(Min) ·Static Drain-Source On-Resistance -RDS(on) = 0.1Ω(Max)@VGS= 10V DESCRIPTION ·Motor drive, DC-DC converter, power switch and solenoid drive.

N-Channel 60 V (D-S) MOSFET

文件：1.32123 Mbytes Page：9 Pages

N-Channel Logic Level Enhancement Mode Field Effect Transistor

HEX non-inverting buffers

DESCRIPTION The HEF4050B provides six non-inverting buffers with high current output capability suitable for driving TTL or high capacitive loads. Since input voltages in excess of the buffers’ supply voltage are permitted, the buffers may also be used to convert logic levels of up to 15 V to s

Hex Inverting,Non-Inverting Buffer

文件：129.6 Kbytes Page：6 Pages

Hex Inverting,Non-Inverting Buffer

文件：129.6 Kbytes Page：6 Pages

Hex Inverting,Non-Inverting Buffer

文件：129.6 Kbytes Page：6 Pages

Hex Inverting,Non-Inverting Buffer

文件：129.6 Kbytes Page：6 Pages