Bus interface registers

DESCRIPTION The 74F821 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of busses carrying parity. FEATURES • High speed parallel registers with positive edge-triggered D-t

8-Bit D-Type Flip-Flop

General Description The 74F825 is an 8-bit buffered register. It has Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming systems. Also included in the 74F825 are multiple enables that allow multi-user control of the interface. Features

Bus interface registers

DESCRIPTION The 74F821 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of busses carrying parity. FEATURES • High speed parallel registers with positive edge-triggered D-t

8-Bit D-Type Flip-Flop

文件：161.59 Kbytes Page：8 Pages

8-Bit D-Type Flip-Flop

文件：63.18 Kbytes Page：6 Pages

High Q, high self-resonant frequency Varnish coated

文件：429.04 Kbytes Page：1 Pages