Arithmetic Logic Unit

DESCRIPTION The 74F381 performs three arithmetic and three logic operations on two 4-bit words, A and B. Three additional Select (S0–S2) input codes force the Function outputs Low or High. Carry Propagate (P) and Generate (G) ouputs are provided for use with the 74F182 Carry Look Ahead Generato

Arithmetic Logic Unit

DESCRIPTION The 74F381 performs three arithmetic and three logic operations on two 4-bit words, A and B. Three additional Select (S0–S2) input codes force the Function outputs Low or High. Carry Propagate (P) and Generate (G) ouputs are provided for use with the 74F182 Carry Look Ahead Generato

Arithmetic Logic Unit

DESCRIPTION The 74F382 performs three arithmetic and three logic operations on two 4-bit words, A and B. Two additional Select (S0–S2) input codes force the Function outputs Low or High. An overflow output is provided for convenience in Two’s Complement arithmetic. FEATURES • Performs six

Arithmetic Logic Unit

DESCRIPTION The 74F382 performs three arithmetic and three logic operations on two 4-bit words, A and B. Two additional Select (S0–S2) input codes force the Function outputs Low or High. An overflow output is provided for convenience in Two’s Complement arithmetic. FEATURES • Performs six

Quad serial adder/subtractor

DESCRIPTION The 74F385 contains four independent adder/subtractor elements with common Clock and Master Reset. Each adder/subtractor contains a sum flop-flop and a carry flip-flop for synchronous operations. Flip-flop state changes occur on the rising edge of the Clock Pulse (CP) input signal. Th

Quad serial adder/subtractor

DESCRIPTION The 74F385 contains four independent adder/subtractor elements with common Clock and Master Reset. Each adder/subtractor contains a sum flop-flop and a carry flip-flop for synchronous operations. Flip-flop state changes occur on the rising edge of the Clock Pulse (CP) input signal. Th

Quad futurebus backplane transceiver

DESCRIPTION The 74F3893 is a quad backplane transceivers and is intended to be used in very high speed bus systems. The 74F3893 interfaces to ‘Backplane Transceiver Logic’ (BTL). BTL features a reduced (1V to 2V) voltage swing for lower power consumption and a series diode on the drivers to

Quad 2-input NAND buffer open collector

FEATURE • Industrial temperature range available (–40°C to +85°C)

Quad 2-input NAND buffer open collector

FEATURE • Industrial temperature range available (–40°C to +85°C)

Arithmetic Logic Unit

Quad serial adder/subtractor

Quad futurebus backplane transceiver

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC GATE NAND OP COL 4CH 2IN 14SO 集成电路（IC） 门和反相器

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC GATE NAND OP COL 4CH 2IN 14SO 集成电路（IC） 门和反相器

Quad 2-input NAND buffer open collector

FEATURE • Industrial temperature range available (–40°C to +85°C)

Quad Two-Input NAND Buffer (Open Collector)

General Description This device contains four independent gates, each of which performs the logic NAND function. The open-collector outputs require external pull-up resistors for proper logical operation.

Quad Two-Input NAND Buffer (Open Collector)

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54F38 74F38 Quad Two-Input NAND Buffer (Open Collector)

文件：393.05 Kbytes Page：10 Pages

Quad Two-Input NAND Buffer (Open Collector)

文件：143.07 Kbytes Page：8 Pages