9-bit interface latch with set and reset 3-State

DESCRIPTION The 74ABT843 Bus interface latch is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • High speed parallel latches • Extra data width for wide address/data pat

9-bit interface latch with set and reset 3-State

DESCRIPTION The 74ABT843 Bus interface latch is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • High speed parallel latches • Extra data width for wide address/data pat

9-bit interface latch with set and reset 3-State

DESCRIPTION The 74ABT843 Bus interface latch is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • High speed parallel latches • Extra data width for wide address/data pat

9-bit interface latch with set and reset 3-State

DESCRIPTION The 74ABT843 Bus interface latch is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • High speed parallel latches • Extra data width for wide address/data pat

9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

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