Dual J-K Flip-Flop with Set and Reset

High–Performance Silicon–Gate CMOS

The MC74HC109 is identical in pinout to the LS109. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

This device consists of two J–K flip–flops with individual set, reset, and clock inputs. Changes at the inputs are reflected at the outputs with the next low–to–high transition of the clock. Both Q and Q outputs are available from each flip–flop.

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard No. 7A

• Chip Complexity: 148 FETs or 37 Equivalent Gates