位置:DS34T101GN+ > DS34T101GN+详情

DS34T101GN+中文资料

厂家型号

DS34T101GN+

文件大小

803.77Kbytes

页面数量

74

功能描述

Single/Dual/Quad/Octal TDM-Over-Packet Chip

通信集成电路 - 若干 Single TDM Over Packet Chip

数据手册

原厂下载下载地址一下载地址二到原厂下载

生产厂商

MAXIM

DS34T101GN+数据手册规格书PDF详情

General Description

These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC compliant devices allow up to eight E1, T1 or serial streams or one high-speed E3, T3, STS-1 or serial stream to be transported transparently over IP, MPLS or Ethernet networks. Jitter and wander of recovered clocks conform to G.823/G.824, G.8261, and TDM specifications. TDM data is transported in up to 64 individually configurable bundles. All standards based TDM-over-packet mapping methods are supported except AAL2. Frame-based serial HDLC data flows are also supported. With built-in full featured E1/T1 framers and LIUs. These ICs encapsulate the TDM-over-packet solution from analog E1/T1 signal to Ethernet MII while preserving options to make use of TDM streams at key intermediate points. The high level of integration available with the DS34T10x devices minimizes cost, board space, and time to market.

Features

♦ Full-Featured IC Includes E1/T1 LIUs and Framers, TDMoP Engine, and 10/100 MAC

♦ Transport of E1, T1, E3, T3 or STS-1 TDM or CBR Serial Signals Over Packet Networks

♦ Full Support for These Mapping Methods: SAToP, CESoPSN, TDMoIP (AAL1), HDLC, Unstructured, Structured, Structured with CAS

♦ Adaptive Clock Recovery, Common Clock, External Clock and Loopback Timing Modes

♦ On-Chip TDM Clock Recovery Machines, One Per Port, Independently Configurable

♦ Clock Recovery Algorithm Handles Network PDV, Packet Loss, Constant Delay Changes, Frequency Changes and Other Impairments

♦ 64 Independent Bundles/Connections

♦ Multiprotocol Encapsulation Supports IPv4, IPv6, UDP, RTP, L2TPv3, MPLS, Metro Ethernet

♦ VLAN Support According to 802.1p and 802.1Q

♦ 10/100 Ethernet MAC Supports MII/RMII/SSMII

♦ Selectable 32-Bit, 16-Bit or SPI Processor Bus

♦ Operates from Only Two Clock Signals, One for Clock Recovery and One for Packet Processing

♦ Glueless SDRAM Buffer Management

♦ Low-Power 1.8V Core, 3.3V I/O

Applications

  TDM Circuit Extension Over PSN

     o Leased-Line Services Over PSN

     o TDM Over GPON/EPON

     o TDM Over Cable

     o TDM Over Wireless

  Cellular Backhaul Over PSN

  Multiservice Over Unified PSN

  HDLC-Based Traffic Transport Over PSN

 

DS34T101GN+产品属性

  • 类型

    描述

  • 型号

    DS34T101GN+

  • 功能描述

    通信集成电路 - 若干 Single TDM Over Packet Chip

  • RoHS

  • 制造商

    Maxim Integrated

  • 类型

    Transport Devices

  • 封装/箱体

    TECSBGA-256

  • 数据速率

    100 Mbps

  • 电源电压-最大

    1.89 V, 3.465 V

  • 电源电压-最小

    1.71 V, 3.135 V

  • 电源电流

    50 mA, 225 mA

  • 最大工作温度

    + 85 C

  • 最小工作温度

    - 40 C

  • 封装

    Tube

更新时间:2025-10-6 13:58:00
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