SINGLE CHANNEL ARINC DECODER

General This circuit receives serial data from a buffered ARINC 429 bus into a 32 bit shift register. At the end of transmission the received word is checked. It is only considered to be “good” if the overall parity is ODD and the length is 32 bits. If the word fails these checks a TRANSMISSION F

SINGLE CHANNEL ARINC DECODER

Radiation and SEE Hardened 3V to 13.2V, 9A Buck Regulator

Features ▪ Electrically screened to DLA SMD 5962-14203 ▪ Acceptance tested to 50krad(Si) (LDR) wafer-bywafer ▪ ±1% reference voltage over line, temperature, and radiation ▪ Integrated MOSFETs 31mΩPFET/21mΩ NFET • 95% peak efficiency ▪ Externally adjustable loop compensation ▪ Supp

Radiation and SEE Hardened 3V to 13.2V, 9A Buck Regulator

Features • Acceptance tested to 50krad(Si) (LDR) wafer-by-wafer • ±1 reference voltage over line, temperature, and radiation • Integrated MOSFETs 31mΩPFET/21mΩ NFET - 95 peak efficiency • Externally adjustable loop compensation • Supports DDR applications (VTT tracks VDDQ/2) - Buffer ampli

Radiation Hardened and SEE Hardened 3V to 13.2V, 6A Buck Regulator

Features • Acceptance tested to 50krad(Si) (LDR) wafer-by-wafer • ±1 reference voltage over line, temperature, and radiation • Integrated MOSFETs 31mΩPFET/21mΩ NFET - 95 peak efficiency • Externally adjustable loop compensation • Supports DDR applications (VTT tracks VDDQ/2) - Buffer ampli

Radiation and SEE Hardened 3V to 13.2V, 9A Buck Regulator

Features • Acceptance tested to 50krad(Si) (LDR) wafer-by-wafer • ±1 reference voltage over line, temperature, and radiation • Integrated MOSFETs 31mΩPFET/21mΩ NFET - 95 peak efficiency • Externally adjustable loop compensation • Supports DDR applications (VTT tracks VDDQ/2) - Buffer ampli

Radiation and SEE Tolerant 3V to 13.2V, 9A Buck Regulator

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