General

This circuit receives serial data from a buffered ARINC 429 bus into a 32 bit shift register. At the end of transmission the received word is checked. It is only considered to be “good” if the overall parity is ODD and the length is 32 bits. If the word fails these checks a TRANSMISSION FAULT flag is set. If the word is ‘good’ the tag bits are loaded into a tag latch and a TAG VALID flag is set. Either internal or external address recognition can be selected according to the state of MODE SELECT.

• 16/24 bit parallel interface

• Automatic address recognition option on 8/10 bits

• Single 5V supply with low power consumption < 50mW

• Full MIL operating range

• Built in parity and word length error detection

• HIGH/LOW speed programmable