SYNCHRONOUS DRAM

GENERAL DESCRIPTION The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456-bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 67,108,864-bit b

封装/外壳：86-TFSOP（0.400"，10.16mm 宽） 包装：托盘 描述：IC DRAM 256MBIT PAR 86TSOP II 集成电路（IC） 存储器

封装/外壳：86-TFSOP（0.400"，10.16mm 宽） 包装：托盘 描述：IC DRAM 256MBIT PAR 86TSOP II 集成电路（IC） 存储器

SYNCHRONOUS DRAM

GENERAL DESCRIPTION The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456-bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 67,108,864-bit b