3.3V 1:10 LVCMOS PLL Clock Generator

3.3V 1:10 LVCMOS PLL Clock Generator The MPC9658 is a 3.3V compatible, 1:10 PLL based clock generator and zero-delay buffer targeted for high performance low-skew clock distribution in mid-range to high-performance telecom, networking and computing applications. With output frequencies up to 250

3.3V 1:10 LVCMOS PLL Clock Generator

The MPC9658 is a 3.3 V compatible, 1:10 PLL based clock generator and zero-delay buffer targeted for high performance low-skew clock distribution in mid-range to high-performance telecom, networking and computing applications. With output frequencies up to 250 MHz and output skews less than 120

LVCMOS Clock Generator

The MPC9658 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9658 requires the connection of the QFB output to the feedback input to close the PLL feedback path (external feedback). With the PLL locked, the output frequency is equal to t Low based low-voltage clock generator\nSupports zero-delay operation\n3.3 V power supply\nGenerates clock signals up to 250 MHz\nMaximum output skew of 120 ps\nDifferential LVPECL reference clock input\nExternal PLL feedback\nDrives up to 20 clock lines\n32-lead LQFP packaging\n32-lead Pb-free Packa;

3.3V 1:10 LVCMOS PLL Clock Generator

封装/外壳：32-LQFP 包装：散装 描述：IC PLL CLK GENERATOR 1:10 32LQFP 集成电路（IC） 时钟发生器，PLL，频率合成器

时钟发生器及支持产品 FSL 1-10 LVCMOS Zero Delay Buffer

封装/外壳：32-LQFP 包装：卷带（TR） 描述：IC PLL CLK GEN 1:10 3.3V 32-LQFP 集成电路（IC） 时钟发生器，PLL，频率合成器

MICROCONTROLLER

PRODUCT OVERVIEW SAM88RCRI PRODUCT FAMILY Samsungs SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offer fast and efficient CPU, a wide range of integrated peripherals, and supports OTP device. A dual address/data bus architecture and bit- or nibble-configurable I/O ports provide a

MICROCONTROLLER

PRODUCT OVERVIEW SAM88RCRI PRODUCT FAMILY Samsungs SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offer fast and efficient CPU, a wide range of integrated peripherals, and supports OTP device. A dual address/data bus architecture and bit- or nibble-configurable I/O ports provide a

Quad Video (Filter) Amplifiers with Input Sync-Tip Clamps

文件：278.4 Kbytes Page：15 Pages

Quad Video (Filter) Amplifiers with Input Sync-Tip Clamps

文件：278.4 Kbytes Page：15 Pages