4-Bit Bistable Latch with Q and Q Output

文件：150.46 Kbytes Page：4 Pages

4-Bit Bistable Latch with Q and Q Output

文件：150.46 Kbytes Page：4 Pages

Quad bistable transparent latch

General description The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC standard no. 7A. The 74HC75 has four bistable latches. The two latches are simultaneously controlled by one of two active

Quad bistable transparent latch

General description The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC standard no. 7A. The 74HC75 has four bistable latches. The two latches are simultaneously controlled by one of two active

4 BIT D TYPE LATCH

DESCRIPTION The M74HC75 is an high speed CMOS 4 BIT D TYPE LATCH fabricated with silicon gate C2MOS technology. ■ HIGH SPEED : tPD = 11ns (TYP.) at VCC = 6V ■ LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C ■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 VCC (MIN.) ■ SYMMETRICAL

4 BIT D TYPE LATCH

DESCRIPTION The M54/74HC75 is a high speed CMOS 4-BIT D-TYPE LATCH fabricated in silicon gate C2MOS technology. ■ HIGH SPEED tPD = 10 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 2 µA (MAX.) AT TA = 25 °C ■ HIGH NOISE IMMUNITY VNIH = VNIL = 28 VCC (MIN.) ■ OUTPUT

4 BIT D TYPE LATCH

DESCRIPTION The M74HC75 is an high speed CMOS 4 BIT D TYPE LATCH fabricated with silicon gate C2MOS technology. ■ HIGH SPEED : tPD = 11ns (TYP.) at VCC = 6V ■ LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C ■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 VCC (MIN.) ■ SYMMETRICAL