3-to-8 Line Decoder

General Description The MM74HC138 decoder utilizes advanced silicon-gate CMOS technology and is well suited to memory address decoding or data routing applications. The circuit features high noise immunity and low power consumption usually associated with CMOS circuitry, yet has speeds comparab

3-to-8 Line Decoder

文件：175.78 Kbytes Page：9 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC DECODER/DEMUX 1X3:8 16SOIC 集成电路（IC） 信号开关，多路复用器，解码器

3-to-8 Line Decoder

General Description The MM74HC138 decoder utilizes advanced silicon-gate CMOS technology and is well suited to memory address decoding or data routing applications. The circuit features high noise immunity and low power consumption usually associated with CMOS circuitry, yet has speeds comparab

3-to-8 Line Decoder

文件：175.78 Kbytes Page：9 Pages

封装/外壳：16-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC DECODER/DEMUX 1X3:8 16TSSOP 集成电路（IC） 信号开关，多路复用器，解码器

3 TO 8 LINE DECODER DEMULTIPLEXER

Description The 74HC138 is a high speed CMOS device. The device accepts a three bit binary weighted address on input pins A0, A1 and A2 and when enabled will produce one active low output with the remaing seven being high. There are two active LOW enable inputs E1 and E2, and one active HIGH en

3-to-8 line decoder/demultiplexer inverting

3-to-8 line decoder/demultiplexer; inverting

GENERAL DESCRIPTION The 74HC/HCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Demultiplexing capability • Multiple input enable for easy expansion • Ideal for memory

1?뭥f?? Decoder/ Demultiplexer High?뭁erformance Silicon?묰ate CMOS

文件：140.61 Kbytes Page：9 Pages

3-to-8 Line Decoder/Demultiplexer; Inverting

文件：229.08 Kbytes Page：5 Pages