ZERO DELAY, LOW SKEW BUFFER

Features • Packaged in 16-pin SOIC • Pb (lead) free package • Zero input-output delay • Four 1X outputs plus four 1/2X outputs • Output to output skew is less than 250 ps • Output clocks up to 133.3 MHz at 3.3 V • Ability to generate 2X the input • Full CMOS outputs with 18 mA output drive

Zero Delay, Low Skew Buffer

The MK2308-2 is a low jitter, low skew, high-performance Phase-Lock Loop (PLL) based zero delay buffer for high-speed applications. Based on Renesas' proprietary low jitter PLL techniques, the device provides eight low skew outputs at speeds up to 133.3MHz at 3.3V. The MK2308-2 includes a bank of fo • Packaged in a 16-pin SOIC\n• Pb (lead) free package\n• Zero input-output delay\n• Four 1X outputs plus four 1/2X outputs\n• Output-to-output skew is less than 250ps\n• Output clocks up to 133.3MHz at 3.3V\n• Ability to generate 2X the input\n• Full CMOS outputs with 18mA output drive capability at;

ZERO DELAY LOW SKEW BUFFER

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3.3V ZERO DELAY CLOCK MULTIPLIER

DESCRIPTION: The IDT2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range o

3.3V ZERO DELAY CLOCK MULTIPLIER

DESCRIPTION: The IDT2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range o

3.3V ZERO DELAY CLOCK MULTIPLIER

DESCRIPTION: The IDT2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range o

3.3V ZERO DELAY CLOCK MULTIPLIER

DESCRIPTION: The IDT2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range o

3.3V ZERO DELAY CLOCK MULTIPLIER

DESCRIPTION: The IDT2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range o