LOW SKEW CMOS PLL 68060 CLOCK DRIVER

The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple locations on a board. The PLL also allows the MC88LV926 to multiply a low frequency input clock and distribute it locally at a higher (2X) system frequency.

Low Skew CMOS PLL 68060 Clock Driver

文件：283.51 Kbytes Page：11 Pages

LOW SKEW CMOS PLL 68060 CLOCK DRIVER

The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple locations on a board. The PLL also allows the MC88LV926 to multiply a low frequency input clock and distribute it locally at a higher (2X) system frequency.

封装/外壳：20-SOIC（0.295"，7.50mm 宽） 包装：托盘 描述：IC CLK BUF CISC 66MHZ 1CIRC 集成电路（IC） 应用特定时钟/定时

Low Skew CMOS PLL 68060 Clock Driver

文件：291.43 Kbytes Page：11 Pages

封装/外壳：20-SOIC（0.295"，7.50mm 宽） 包装：托盘 描述：IC CLK BUF CISC 66MHZ 1CIRC 集成电路（IC） 应用特定时钟/定时