1-of-8 Decoder/Demultiplexer with LSTTL Compatible Inputs

The MC54/74HC138A is identical in pinout to the LS138. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC138A decodes a three–bit Address to one–of–eight active–low outputs. This device features three Chip Select input

1-of-8 Decoder/Demultiplexer with LSTTL Compatible Inputs

The MC74HCT138A is identical in pinout to the LS138. The HCT138A may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. The HCT138A decodes a three−bit Address to one−of−eight active−lot outputs. This device features three Chip Select inputs, two active−lo

1?뭥f?? Decoder/ Demultiplexer with LSTTL Compatible Inputs High?뭁erformance Silicon?묰ate CMOS

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封装/外壳：16-DIP（0.300"，7.62mm） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC DECODER/DEMUX 1X3:8 16DIP 集成电路（IC） 信号开关，多路复用器，解码器

封装/外壳：16-DIP（0.300"，7.62mm） 包装：托盘 描述：IC DECODER/DEMUX 1X3:8 16DIP 集成电路（IC） 信号开关，多路复用器，解码器

1?뭥f?? Decoder/ Demultiplexer with LSTTL Compatible Inputs High?뭁erformance Silicon?묰ate CMOS

文件：102.65 Kbytes Page：8 Pages

3-to-8 line decoder/demultiplexer inverting

3-to-8 line decoder/demultiplexer; inverting

1. General description The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple ena

3-to-8 line decoder/demultiplexer; inverting

GENERAL DESCRIPTION The 74HC/HCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Demultiplexing capability • Multiple input enable for easy expansion • Ideal for memory

3-to-8 line decoder/demultiplexer; inverting

3 TO 8 LINE DECODER DEMULTIPLEXER

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