Octal 3?뭆tate Noninverting Transparent Latch High?뭁erformance Silicon?묰ate CMOS

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Octal 3?뭆tate Noninverting Transparent Latch High?뭁erformance Silicon?묰ate CMOS

文件：118.52 Kbytes Page：8 Pages

封装/外壳：20-SOIC（0.209"，5.30mm 宽） 包装：卷带（TR） 描述：IC LATCH TRANSP OCTAL 20-SOEIAJ 集成电路（IC） 锁存器

Octal D-type transparent latch; 3-state

GENERAL DESCRIPTION The 74HC/HCT573 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Inputs and outputs on opposite sides of package allowing easy interface with microp

Octal D-type transparent latch; 3-state

1. General description The 74HC573; 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will

Octal 3-State Noninverting Transparent Latch(High-Performance Silicon-Gate CMOS)

The SL74HC573 is identical in pinout to the LS/ALS573. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When

Octal D-type transparent latch 3-state

GENERAL DESCRIPTION The 74HC/HCT573 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Inputs and outputs on opposite sides of package allowing easy interface with microp

Octal 3-State Noninverting Transparent Latch

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