Quad D Flip?묯lop with Common Clock and Reset High?뭁erformance Silicon?묰ate CMOS

文件：121.01 Kbytes Page：10 Pages

Quad D Flip?묯lop with Common Clock and Reset High?뭁erformance Silicon?묰ate CMOS

文件：121.01 Kbytes Page：10 Pages

封装/外壳：16-SOIC（0.209"，5.30mm 宽） 功能：主复位 包装：卷带（TR） 描述：IC FF D-TYPE SNGL 4BIT 16SOEIAJ 集成电路（IC） 触发器

Quad D-type flip-flop with reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT175 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT175 have four edge-triggered, D-type flip-flops with individual D inputs and both Q and Q o

Quad D-type flip-flop with reset; positive-edge trigger

1. General description The 74HC175; 74HCT175 is a quad positive-edge triggered D-type flip-flop with individual data inputs (Dn) and complementary outputs (Qn and Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set

High Speed CMOS Logic

Description The 74HC175 is fabricated using a 2.5μm 5V CMOS process and consists of four D-Type flip–flops each with separate D input and common Reset and Clock inputs. The logic level present at the “D” input is transferred to the Q output during the positive-going transition of the clock p

High Speed CMOS Logic

Features Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Low Input Current: 1μA High Noise Immunity Characteristics of CMOS Operating Voltage Range: 2.0 to 6.0 V Direct drop-in replacement for obsolete components in long term programs.

Quad D-Type Flip-Flop With Clear

Features n Typical propagation delay: 15 ns n Wide operating supply voltage range: 2–6V n Low input current: 1 mA maximum n Low quiescent supply current: 80 mA maximum (74HC) n High output drive current: 4 mA minimum (74HC) General Description The MM74HC175 high speed D-type flip-flop wit