DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS

2-V to 6-V Operation Fully Static Operation Buffered Inputs Common Reset Positive-Edge Clocking Balanced Propagation Delay and Transition Times High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V Packaged in Ceramic (F) DIP Package and Also Available in Chip Form (H)

HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS

Controlled Baseline − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −40°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† Fully Static Operation Buffered Inputs Common Reset

High-Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs

文件：347.51 Kbytes Page：14 Pages

High-Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs

文件：497.87 Kbytes Page：16 Pages

High-Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs

文件：528.36 Kbytes Page：16 Pages