Quad D Flip-Flop with Common Clock and Reset

文件：200.41 Kbytes Page：7 Pages

Quad D Flip-Flop with Common Clock and Reset

Quad D Flip-Flop with Common Clock and Reset

Quad D Flip-Flop with Common Clock and Reset

文件：200.41 Kbytes Page：7 Pages

High Speed CMOS Logic

Description The 54HC175 is fabricated using a 2.5μm 5V CMOS process and consists of four D-Type flip–flops each with separate D input and common Reset and Clock inputs. The logic level present at the “D” input is transferred to the Q output during the positive-going transition of the clock p

High Speed CMOS Logic

Features:  Output Drive Capability: 10 LSTTL Loads  Outputs Directly Interface to CMOS, NMOS, and TTL  Low Input Current: 1μA  High Noise Immunity Characteristics of CMOS  Operating Voltage Range: 2.0 to 6.0 V  Direct drop-in replacement for obsolete components in long term programs.

High-Speed CMOS Logic Quad D-Type Flip-Flop with Reset

文件：422.08 Kbytes Page：14 Pages

High-Speed CMOS Logic Quad D-Type Flip-Flop with Reset

文件：562.42 Kbytes Page：15 Pages

High-Speed CMOS Logic Quad D-Type Flip-Flop with Reset

文件：278.1 Kbytes Page：12 Pages