5V ECL Programmable Delay Chip

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封装/外壳：28-LCC（J 形引线） 功能：可编程 包装：卷带（TR） 描述：IC DELAY LINE 128TAP PROG 28PLCC 集成电路（IC） 延迟线

PROGRAMMABLE DELAY CHIP

5V ECL Programmable Delay Chip

文件：150.75 Kbytes Page：11 Pages

封装/外壳：28-LCC（J 形引线） 功能：可编程 包装：卷带（TR） 描述：IC DELAY LINE 128TAP PROG 28PLCC 集成电路（IC） 延迟线

5V ECL Programmable Delay Chip

文件：150.75 Kbytes Page：11 Pages

5V ECL Programmable Delay Chip

文件：150.75 Kbytes Page：11 Pages

5V ECL Programmable Delay Chip

文件：183.29 Kbytes Page：11 Pages

PROGRAMMABLE DELAY CHIP

Description The MC10E/100E195 is a programmable delay chip (PDC) designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in the logic symbol. The first two

PROGRAMMABLE DELAY CHIP

DESCRIPTION The SY10/100E195 are programmable delay chips (PDCs) designed primarily for clock de-skewing and timing adjustment. They provide variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in the logic diagram. The first tw

PROGRAMMABLE DELAY CHIP

DESCRIPTION The SY10/100E195 are programmable delay chips (PDCs) designed primarily for clock de-skewing and timing adjustment. They provide variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in the logic diagram. The first tw

PROGRAMMABLE DELAY CHIP

DESCRIPTION The SY10/100E195 are programmable delay chips (PDCs) designed primarily for clock de-skewing and timing adjustment. They provide variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in the logic diagram. The first tw

PROGRAMMABLE DELAY CHIP

文件：77.62 Kbytes Page：8 Pages