3.3V ECL 첨4 Divider

文件：140.92 Kbytes Page：8 Pages

3.3V ECL 첨4 Divider

文件：140.92 Kbytes Page：8 Pages

3.3 V ECL /4 Divider

文件：159.14 Kbytes Page：7 Pages

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC DIVIDER DIV X4 DIFF 8-SOIC 集成电路（IC） 计数器，除法器

ECL/PECL 첨4 Divider

DESCRIPTION The AZ10/100LVEL33 is an integrated ÷4 divider. The RESET pin is asynchronous and clears the output (Q Low, Q¯ High) on the rising edge. Upon power-up, the internal flip-flop will be in a random logic state. RESET allows for the synchronization of multiple LVEL33’s in a system. FEATU

ECL/PECL 첨4 Divider

DESCRIPTION The AZ10/100LVEL33 is an integrated ÷4 divider. The RESET pin is asynchronous and clears the output (Q Low, Q¯ High) on the rising edge. Upon power-up, the internal flip-flop will be in a random logic state. RESET allows for the synchronization of multiple LVEL33’s in a system. FEATU

ECL/PECL 첨4 Divider

DESCRIPTION The AZ10/100LVEL33 is an integrated ÷4 divider. The RESET pin is asynchronous and clears the output (Q Low, Q¯ High) on the rising edge. Upon power-up, the internal flip-flop will be in a random logic state. RESET allows for the synchronization of multiple LVEL33’s in a system. FEATU

ECL/PECL 첨4 Divider

文件：113.91 Kbytes Page：8 Pages

ECL/PECL 첨4 Divider

文件：113.91 Kbytes Page：8 Pages