LVTTL/LVCOMS to Differential LVECL Translator

Description The MC100EPT24 is a LVTTL/LVCMOS to differential LVECL translator. Because LVECL levels and LVTTL/LVCMOS levels are used, a −3.3 V, +3.3 V and ground are required. The small outline 8−lead package and the single gate of the EPT24 makes it ideal for those applications where space, perf

Clock Management Design Using Low Skew and Low Jitter Devices

Why Do We Need Clock Management? Can you imagine the chaos in our world if our clocks or watches were not synchronized to Greenwich Mean Time? How would trains, buses, and airplanes run on schedule? The miniseries Longitude was the story of a man who made a major technological breakthrough by inv

3.3V LVTTL/LVCMOS to Differential LVECL Translator

文件：135.86 Kbytes Page：8 Pages

LVTTL/LVCOMS to Differential LVECL Translator

Description The MC100EPT24 is a LVTTL/LVCMOS to differential LVECL translator. Because LVECL levels and LVTTL/LVCMOS levels are used, a −3.3 V, +3.3 V and ground are required. The small outline 8−lead package and the single gate of the EPT24 makes it ideal for those applications where space, perf

3.3V LVTTL/LVCMOS to Differential LVECL Translator

文件：135.86 Kbytes Page：8 Pages