첨2,첨4,첨8 Clock Generation Chip

Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. Features • 50 ps Output-to-Output Skew • Synchronous Enable/Disable • Master Reset for Synchronization • PECL Mode Operating Range: VCC = 4.2

5V ECL 첨2, 첨4, 첨8 Clock Generation Chip

Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. Features • 50 ps Output-to-Output Skew • Synchronous Enable/Disable • Master Reset for Synchronization • PECL Mode Operating Range: VCC = 4.2

5.0 V ECL ÷2, ÷4, ÷8 Clock Generation Chip

The MC10/100EL34 is a low skew divide by 2, divide by 4, divide by 8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by ei • 50ps Output-to-Output Skew\n• Synchronous Enable/Disable\n• Master Reset for Synchronization\n• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V\n• NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V\n• Internal Input Pulldown Resistors on CLK(s), ENbar, and MR\n• Pb-Fre;

5V ECL 첨2, 첨4, 첨8 Clock Generation Chip

文件：133.17 Kbytes Page：8 Pages

첨2,첨4,첨8 Clock Generation Chip

Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. Features • 50 ps Output-to-Output Skew • Synchronous Enable/Disable • Master Reset for Synchronization • PECL Mode Operating Range: VCC = 4.2

5V ECL 첨2, 첨4, 첨8 Clock Generation Chip

Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. Features • 50 ps Output-to-Output Skew • Synchronous Enable/Disable • Master Reset for Synchronization • PECL Mode Operating Range: VCC = 4.2

5V ECL 첨2, 첨4, 첨8 Clock Generation Chip

Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. Features • 50 ps Output-to-Output Skew • Synchronous Enable/Disable • Master Reset for Synchronization • PECL Mode Operating Range: VCC = 4.2

첨2,첨4,첨8 Clock Generation Chip

Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. Features • 50 ps Output-to-Output Skew • Synchronous Enable/Disable • Master Reset for Synchronization • PECL Mode Operating Range: VCC = 4.2

5V ECL 첨2, 첨4, 첨8 Clock Generation Chip

文件：133.17 Kbytes Page：8 Pages

5V ECL 첨2, 첨4, 첨8 Clock Generation Chip

文件：133.17 Kbytes Page：8 Pages

Clock Generation Chip

文件：173.77 Kbytes Page：9 Pages

5V ECL 첨2, 첨4, 첨8 Clock Generation Chip

文件：133.17 Kbytes Page：8 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC CLOCK GEN ECL 2/4/8 16-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC CLOCK GEN ECL 2/4/8 16-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

5V ECL 첨2, 첨4, 첨8 Clock Generation Chip

文件：133.17 Kbytes Page：8 Pages

5V/3.3V 첨2, 첨4, 첨8 CLOCK GENERATION CHIP

DESCRIPTION The SY10/100EL34/L are low skew ÷2, ÷4, ÷8 clock generation chips designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a di

5V/3.3V 첨2, 첨4, 첨8 CLOCK GENERATION CHIP

DESCRIPTION The SY10/100EL34/L are low skew ÷2, ÷4, ÷8 clock generation chips designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a di