Differential PECL/ECL/LVPECL/LVECL Receiver/Driver

General Description The MAX9321B low-skew differential receiver/driver is designed for clock and data distribution. The differential input can be adapted to accept a single-ended input by connecting the on-chip VBB supply to an input as a reference voltage. The MAX9321B features ultra-low pr

差分PECL/ECL/LVPECL/LVECL接收器/驱动器

Differential PECL/ECL/LVPECL/LVECL Receiver/Driver

General Description The MAX9321B low-skew differential receiver/driver is designed for clock and data distribution. The differential input can be adapted to accept a single-ended input by connecting the on-chip VBB supply to an input as a reference voltage. The MAX9321B features ultra-low pr

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：托盘 描述：IC CLK DATA DRVR 1:1 3GHZ 8SOIC 集成电路（IC） 时钟缓冲器，驱动器

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：DIFFERENTIAL PECL/ECL/LVPECL/LVE 集成电路（IC） 时钟缓冲器，驱动器

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