四路LVDS线接收器，内部端接，引脚按信号流向排列

Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout

文件：231.93 Kbytes Page：12 Pages

Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout

文件：231.93 Kbytes Page：12 Pages

封装/外壳：16-TSSOP（0.173"，4.40mm 宽） 包装：管件 描述：IC RECEIVER 0/4 16TSSOP 集成电路（IC） 驱动器，接收器，收发器

封装/外壳：16-TSSOP（0.173"，4.40mm 宽） 包装：管件 描述：IC RECEIVER 0/4 16TSSOP 集成电路（IC） 驱动器，接收器，收发器

Dual, 16–Bit, 1230 MSPS, TxDAC Digital-to-Analog Converter

FEATURES ► Flexible LVDS interface allows word, byte, or nibble load ► Single-carrier W-CDMA ACLR = 82 dBc at 122.88 MHz IF ► Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω ► Integrated 2×/4×/8× interpolator/complex modulator allows carrier placement anywhere in the DAC bandwi

Dual, 16-Bit, 1200 MSPS, TxDAC짰 Digital-to-Analog Converter

GENERAL DESCRIPTION The AD9122 is a dual 16-bit, high dynamic range, digital-to analog converter (DAC) that provides a sample rate of 1200 MSPS, permitting a multicarrier generation up to the Nyquist frequency. It includes features optimized for direct conversion transmit applications, includin

Programmable DC Power Supplies

文件：800.12 Kbytes Page：3 Pages

High Dynamic Range RF Transmitter Signal Chain Using Single External Frequency Reference for DAC Sample Clock and IQ Modulator LO Generation

文件：707.5 Kbytes Page：8 Pages

Interfacing the ADL5375 I/Q Modulator to the AD9122 Dual Channel, 1.2 GSPS High Speed DAC

文件：563.58 Kbytes Page：9 Pages