Overvoltage Protection with USB Charger Detection, LDO, and ESD Protection on D/D-

General Description The MAX14529E/MAX14530E are overvoltage-protection devices with USB charger detection, a low-dropout (LDO) regulator, and ESD protection. These devices feature a low 35mΩ (typ) RON internal FET switch and protect low-voltage systems against voltage faults up to 28V. When the i

Overvoltage Protection with USB Charger Detection, LDO, and ESD Protection on D/D-

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Overvoltage Protection with USB Charger Detection, LDO, and ESD Protection on D/D-

General Description The MAX14529E/MAX14530E are overvoltage-protection devices with USB charger detection, a low-dropout (LDO) regulator, and ESD protection. These devices feature a low 35mΩ (typ) RON internal FET switch and protect low-voltage systems against voltage faults up to 28V. When the i

DUAL 5-INPUT MAJORITY LOGIC GATE

The MC14530B dual five–input majority logic gate is constructed with P–channel and N–channel enhancement mode devices in a single monolithic structure. Combinational and sequential logic expressions are easily implemented with the majority logic gate, often resulting in fewer components than obtai

DUAL 5-INPUT MAJORITY LOGIC GATE

The MC14530B dual five–input majority logic gate is constructed with P–channel and N–channel enhancement mode devices in a single monolithic structure. Combinational and sequential logic expressions are easily implemented with the majority logic gate, often resulting in fewer components than obtai

DUAL 5-INPUT MAJORITY LOGIC GATE

The MC14530B dual five–input majority logic gate is constructed with P–channel and N–channel enhancement mode devices in a single monolithic structure. Combinational and sequential logic expressions are easily implemented with the majority logic gate, often resulting in fewer components than obtai

DUAL 5-INPUT MAJORITY LOGIC GATE

The MC14530B dual five–input majority logic gate is constructed with P–channel and N–channel enhancement mode devices in a single monolithic structure. Combinational and sequential logic expressions are easily implemented with the majority logic gate, often resulting in fewer components than obtai