可编程逻辑器件(CPLD/FPGA)

High-Density EE CMOS Programmable Logic

GENERAL DESCRIPTION The MACH110 is a member of AMD’s high-performance EE CMOS MACH 1 family. This device has approximately three times the logic macrocell capability of the popular PAL22V10 without loss of speed. DISTINCTIVE CHARACTERISTICS ■ 44 Pins ■ 32 Macrocells ■ 12 ns tPD Commercial 14

High-Density EE CMOS Programmable Logic

GENERAL DESCRIPTION The MACH110 is a member of our high-performance EE CMOS MACH 1 family. This device has approximately three times the logic macrocell capability of the popular PAL22V10 without loss of speed. DISTINCTIVE CHARACTERISTICS ■ 44 Pins ■ 32 Macrocells ■ 12 ns tPD Commercial 14 ns

SCR Chip

文件：292.16 Kbytes Page：2 Pages

Chip - double mesa SCRs of reverse blocking high-voltage

文件：180.52 Kbytes Page：3 Pages

Single Loop Controller Series MULTI-FUNCTION PID CONTROLLER

文件：437.84 Kbytes Page：12 Pages