OCTAL BUS TRANSCEIVER3-STATE: HCT245 NON INVERTING HCT640 INVERTING, HCT643 INVERTING/NON INVERTING

DESCRIPTION The M54/74HCT245, HCT640 and HCT643 utilise silicon gate C2MOS technology to achive operating speeds eqivalent to LSTTL devices. ■ HIGH SPEED tPD = 10 ns (TYP.) at VCC = 5V ■ LOW POWER DISSIPATION ICC = 4 µA (MAX.) at TA = 25 °C ■ COMPATIBLE WITH TTL OUTPUTS VIH

OCTAL BUS TRANSCEIVER3-STATE: HCT245 NON INVERTING HCT640 INVERTING, HCT643 INVERTING/NON INVERTING

DESCRIPTION The M54/74HCT245, HCT640 and HCT643 utilise silicon gate C2MOS technology to achive operating speeds eqivalent to LSTTL devices. ■ HIGH SPEED tPD = 10 ns (TYP.) at VCC = 5V ■ LOW POWER DISSIPATION ICC = 4 µA (MAX.) at TA = 25 °C ■ COMPATIBLE WITH TTL OUTPUTS VIH

OCTAL BUS TRANSCEIVER3-STATE: HCT245 NON INVERTING HCT640 INVERTING, HCT643 INVERTING/NON INVERTING

DESCRIPTION The M54/74HCT245, HCT640 and HCT643 utilise silicon gate C2MOS technology to achive operating speeds eqivalent to LSTTL devices. ■ HIGH SPEED tPD = 10 ns (TYP.) at VCC = 5V ■ LOW POWER DISSIPATION ICC = 4 µA (MAX.) at TA = 25 °C ■ COMPATIBLE WITH TTL OUTPUTS VIH

OCTAL BUS TRANSCEIVER3-STATE: HCT245 NON INVERTING HCT640 INVERTING, HCT643 INVERTING/NON INVERTING

DESCRIPTION The M54/74HCT245, HCT640 and HCT643 utilise silicon gate C2MOS technology to achive operating speeds eqivalent to LSTTL devices. ■ HIGH SPEED tPD = 10 ns (TYP.) at VCC = 5V ■ LOW POWER DISSIPATION ICC = 4 µA (MAX.) at TA = 25 °C ■ COMPATIBLE WITH TTL OUTPUTS VIH

Octal bus transceiver; 3-state; true/inverting

GENERAL DESCRIPTION The 74HC/HCT643 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Octal bidirectional bus interface • True and inverting 3-state outputs • Output capabilit

Octal Bus Transceivers (with 3-state outputs)

Description Both the HD74HCT640 and the HD74HCT643 have one active low enable input (G), and a direction control (DIR). When the DIR input is high, data flows from the A inputs to the B outputs. When DIR is low, data flows from B to A. The HD74HCT640 transfers inverted data from one bus to the o

Inverting Octal TRI-STATE Transceiver

文件：140.5 Kbytes Page：4 Pages

Inverting Octal TRI-STATE Transceiver

文件：140.5 Kbytes Page：4 Pages