OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HC563 INVERTING - HC573 NON INVERTING

DESCRIPTION The M54/74HC563 and M54HC573 are high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with in silicon gate C2MOS technology. These ICs archive the high speed operation similar to equivalent LSTTL while maintaning the CMOS low power dissipation. ■ HIGH SPEED tPD = 13 ns (T

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

DESCRIPTION The M74HC573 is an high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with silicon gate C2MOS technology ■ HIGH SPEED: tPD = 13ns (TYP.) at VCC = 6V ■ LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C ■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 VCC (MIN.) ■ SYMMETRICAL OUTPU

封装/外壳：20-SOIC（0.295"，7.50mm 宽） 包装：卷带（TR） 描述：IC DTYPE LATCH 3-ST OCTAL 20SOP 集成电路（IC） 锁存器

Octal D-type transparent latch; 3-state

1. General description The 74HC573; 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will

Octal D-type transparent latch; 3-state

GENERAL DESCRIPTION The 74HC/HCT573 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Inputs and outputs on opposite sides of package allowing easy interface with microp

Octal D-type transparent latch 3-state

GENERAL DESCRIPTION The 74HC/HCT573 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Inputs and outputs on opposite sides of package allowing easy interface with microp

Octal 3-State Noninverting Transparent Latch(High-Performance Silicon-Gate CMOS)

The SL74HC573 is identical in pinout to the LS/ALS573. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When

Octal 3-State Noninverting Transparent Latch

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