HC4020 14 STAGE BINARY COUNTER HC4040 12 STAGE BINARY COUNTER

DESCRIPTION The M54/74HC4020/HC4040 are high speed CMOS 14/12-STAGE BINARY COUNTER fabricated in silicon gate C2MOS technology. They have the same high speed performance of LSTTL combined with true CMOS low consumption. ■ HIGH SPEED fMAX = 73 MHz (TYP.) at VCC = 5 V ■ LOW POWER DISSIPATION ICC

12 STAGE BINARY COUNTER

DESCRIPTION The M54/74HC4020/HC4040 are high speed CMOS 14/12-STAGE BINARY COUNTER fabricated in silicon gate C2MOS technology. They have the same high speed performance of LSTTL combined with true CMOS low consumption. ■ HIGH SPEED fMAX = 73 MHz (TYP.) at VCC = 5 V ■ LOW POWER DISSIPATION ICC

12-stage binary ripple counter

General description The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchr

High Speed CMOS Logic

Features  Output Drive Capability: 10 LSTTL Loads  Low Input Current: 1μA  Outputs directly interface CMOS, NMOS and TTL  Operating Voltage Range: 2V to 6V  CMOS High Noise Immunity  Function compatible with CD4040B

12-stage binary ripple counter

1. General description The 74HC4040; 74HCT4040 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stage

12-stage binary ripple counter

General description The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchr

12-stage binary ripple counter

1. General description The 74HC4040; 74HCT4040 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stage