3 TO 8 LINE DECODER LATCH

DESCRIPTION The M74HC237 is an high speed CMOS 3 TO 8 LINE DECODER fabricated with silicon gate C2MOS technology. ■ HIGH SPEED: tPD = 16ns (TYP.) at VCC = 6V ■ LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C ■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 VCC (MIN.) ■ SYMMETRICAL OUTPUT IMPEDANCE:

3 TO 8 LINE DECODER LATCH

DESCRIPTION The M54/74HC237 is a high speed CMOS 3 TO 8 LINE DECODER LATCH fabricated in silicon gate C2MOS technology. ■ HIGH SPEED tPD = 12 ns (TYP.) at VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C ■ HIGH NOISE IMMUNITY VNIH = VNIL = 28 VCC (MIN.) ■ OUTPUT DRIVE CAPABI

3-to-8 line decoder, demultiplexer with address latches

1. General description The 74HC237 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC237 essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE = LOW), the 74HC237 acts as a 3-to-8 active LOW decode

3-to-8 line decoder/demultiplexer with address latches

GENERAL DESCRIPTION The 74HC/HCT237 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Combines 3-to-8 decoder with 3-bit latch • Multiple input enable for easy expansion or i

3-to-8 line decoder, demultiplexer with address latches

GENERAL DESCRIPTION The 74HC/HCT237 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Combines 3-to-8 decoder with 3-bit latch • Multiple input enable for easy expansion or i

3-to-8 line decoder, demultiplexer with address latches

3-to-8 line decoder, demultiplexer with address latches