DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

DESCRIPTION The M54/74HC109 is a high speed CMOS DUAL JK FLIP-FLOP WITH PRESET AND CLEAR fabricated in silicon gate C2MOS technology. ■ HIGH SPEED fMAX = 63 MHz (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 2 µA (MAX.) AT TA = 25 °C ■ HIGH NOISE IMMUNITY VNIH = VNIL = 2

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：187.76 Kbytes Page：12 Pages

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

DESCRIPTION The M54/74HC109 is a high speed CMOS DUAL JK FLIP-FLOP WITH PRESET AND CLEAR fabricated in silicon gate C2MOS technology. ■ HIGH SPEED fMAX = 63 MHz (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 2 µA (MAX.) AT TA = 25 °C ■ HIGH NOISE IMMUNITY VNIH = VNIL = 2

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

DESCRIPTION The M54/74HC109 is a high speed CMOS DUAL JK FLIP-FLOP WITH PRESET AND CLEAR fabricated in silicon gate C2MOS technology. ■ HIGH SPEED fMAX = 63 MHz (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 2 µA (MAX.) AT TA = 25 °C ■ HIGH NOISE IMMUNITY VNIH = VNIL = 2

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

DESCRIPTION The M54/74HC109 is a high speed CMOS DUAL JK FLIP-FLOP WITH PRESET AND CLEAR fabricated in silicon gate C2MOS technology. ■ HIGH SPEED fMAX = 63 MHz (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 2 µA (MAX.) AT TA = 25 °C ■ HIGH NOISE IMMUNITY VNIH = VNIL = 2

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：187.76 Kbytes Page：12 Pages

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：187.76 Kbytes Page：12 Pages

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：187.76 Kbytes Page：12 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF JK TYPE DUAL 1BIT 16SOP 集成电路（IC） 触发器

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：卷带（TR） 描述：IC FF JK TYPE DUAL 1BIT 16SOP 集成电路（IC） 触发器

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：187.76 Kbytes Page：12 Pages

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：187.76 Kbytes Page：12 Pages

Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)