5V, 1 Mbit 128Kb x8 Low Power SRAM with Output Enable

DESCRIPTION The M68Z128 is a 1 Mbit (1,048,576 bit) CMOS SRAM, organized as 131,072 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 5V ±10 supply, and all inputs and outputs

5V, 1 Mbit 128Kb x8 Low Power SRAM with Output Enable

DESCRIPTION The M68Z128 is a 1 Mbit (1,048,576 bit) CMOS SRAM, organized as 131,072 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 5V ±10 supply, and all inputs and outputs

3V, 1 Mbit 128Kb x8 Low Power SRAM with Output Enable

DESCRIPTION The M68Z128W is a 1 Mbit (1,048,576 bit) Fast CMOS SRAM, organized as 131,072 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 3.0V (+0.6V / –0.3V) supply, and al

3V, 1 Mbit 128Kb x8 Low Power SRAM with Output Enable

DESCRIPTION The M68Z128W is a 1 Mbit (1,048,576 bit) Fast CMOS SRAM, organized as 131,072 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 3.0V (+0.6V / –0.3V) supply, and al