4 Mbit (512K x8) 3.0V Asynchronous SRAM

SUMMARY DESCRIPTION The M68AW511A is a 4 Mbit (4,194,304 bit) CMOS SRAM, organized as 524,288 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.7 to 3.6V supply. FEATURES S