1152 x 8-BIT LINE MEMORY FIFO

DESCRIPTION The M66252P/FP is a high-speed line memory with a FIFO (First In First Out) structure of 1152-word × 8-bit configuration which uses high-performance silicon gate CMOS process technology. It has separate clock, enable and reset signals for write and read and is most suitable as a buff

1152*8-BIT LINE MEMORY(FIFO)

DESCRIPTION The M66252P/FP is a high-speed line memory with a FIFO (First In First Out) structure of 1152-word × 8-bit configuration which uses high-performance silicon gate CMOS process technology. It has separate clock, enable and reset signals for write and read and is most suitable as a buff

1152*8-BIT LINE MEMORY(FIFO)

1152*8-BIT LINE MEMORY(FIFO)

DESCRIPTION The M66252P/FP is a high-speed line memory with a FIFO (First In First Out) structure of 1152-word × 8-bit configuration which uses high-performance silicon gate CMOS process technology. It has separate clock, enable and reset signals for write and read and is most suitable as a buff

N-Channel 25 V (D-S) MOSFET

FEATURES • 100 Rg and UIS Tested • DT-Trench Power MOSFET APPLICATIONS • High power density DC/DC • Load switching • Battery management

Low input current requirement: 0.5mA

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