DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

DESCRIPTION The M54HC112 is an high speed CMOS DUAL J-K FLIP-FLOP WITH PRESET AND CLEAR fabricated with silicon gate C2MOS technology. The M54HC112 dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs for each flip-flop. When the clock goes high, the inputs ar

RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：254.42 Kbytes Page：11 Pages

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

DESCRIPTION The M54HC112 is an high speed CMOS DUAL J-K FLIP-FLOP WITH PRESET AND CLEAR fabricated with silicon gate C2MOS technology. The M54HC112 dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs for each flip-flop. When the clock goes high, the inputs ar

RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：254.42 Kbytes Page：11 Pages

RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：254.42 Kbytes Page：11 Pages

RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：254.42 Kbytes Page：11 Pages

RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：254.42 Kbytes Page：11 Pages

RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：254.42 Kbytes Page：11 Pages

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

文件：445.61 Kbytes Page：14 Pages

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

文件：445.61 Kbytes Page：14 Pages

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

文件：445.61 Kbytes Page：14 Pages

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

文件：445.61 Kbytes Page：14 Pages