DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

DESCRIPTION The M54HC112 is an high speed CMOS DUAL J-K FLIP-FLOP WITH PRESET AND CLEAR fabricated with silicon gate C2MOS technology. The M54HC112 dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs for each flip-flop. When the clock goes high, the inputs ar

RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：254.42 Kbytes Page：11 Pages

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

DESCRIPTION The M54HC112 is an high speed CMOS DUAL J-K FLIP-FLOP WITH PRESET AND CLEAR fabricated with silicon gate C2MOS technology. The M54HC112 dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs for each flip-flop. When the clock goes high, the inputs ar

RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：254.42 Kbytes Page：11 Pages

RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：254.42 Kbytes Page：11 Pages

RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：254.42 Kbytes Page：11 Pages

RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：254.42 Kbytes Page：11 Pages

RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：254.42 Kbytes Page：11 Pages

High Speed CMOS Logic

Features: Output Drive Capability: 10 LSTTL Loads Bus Drive Capability: 15 LSTTL Loads Low Input Current: 1μA Outputs directly interface CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 54LS112 Full Military Temperature Range.

High Speed CMOS Logic

文件：683.61 Kbytes Page：6 Pages

High Speed CMOS Logic

文件：440.21 Kbytes Page：6 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：643.79 Kbytes Page：18 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：346.89 Kbytes Page：13 Pages