VCSO BASED CLOCK PLL

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VCSO Based Clock PLL

封装/外壳：36-CLCC 包装：卷带（TR） 描述：IC PLL FREQ TRANSLATOR 36CLCC 集成电路（IC） 时钟发生器，PLL，频率合成器

封装/外壳：36-CLCC 包装：卷带（TR） 描述：IC PLL FREQ TRANSLATOR 36CLCC 集成电路（IC） 时钟发生器，PLL，频率合成器

VCSO BASED CLOCK PLL

文件：431.78 Kbytes Page：10 Pages

线对板/线对线连接器

线对板/线对线连接器

HIGH VOLTAGE CAPACITORS MONOLITHIC CERAMIC TYPE

FIXED SIP DELAY LINE TR 1ns

FUNCTIONAL DESCRIPTION The 2020- and 2021-series devices are fixed, single-input, single-output, passive delay lines. The signal input (IN) is reproduced at the output (OUT), shifted by a time (TD) given by the device dash number. The characteristic impedance of the lines is nominally 50 ohms. Th

Directional Couplers Mini, Octave Bandwidth

Description These miniature couplers are designed to provide sampling of the RF Power propagating in one direction on a transmission line. Features • Smallest and Lightest Couplers Available • 0.5 through 18 GHz, including Wideband Units • High Directivity - Low VSWR • Meets MIL-E-5400 Envir

Directional Couplers Mini, Octave Brandwidth

Aluminum Electrolytic Capacitors

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